lockit.tan.rpt

来自「altera FPGA/CPLD高级篇(VHDL源代码)」· RPT 代码 · 共 194 行 · 第 1/5 页

; Clock Setup: 'fir_clock' ; N/A   ; None          ; 255.56 MHz ( period = 3.913 ns ) ; fir_top:inst2|fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|q_b[0]~Iporta_datain_reg0    ; fir_top:inst2|fir_top_st:fir_top_st_component|ram_lut:Ur1_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_rs41:auto_generated|q_b[0]~Iporta_memory_reg0 ;
+--------------------------+-------+---------------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                               ;
+---------------------------------------------------------------------------------------------------------------------------------------
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; fir_clock       ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
; fifo_clk        ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'fir_clock'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                          ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; Slack                                   ; Actual fmax (period)                                       ; From                                                                                                                                                                  ; To                                                                                                                                                                    ; From Clock ; To Clock  ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+-----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 255.56 MHz ( period = 3.913 ns )                           ; fir_top:inst1|fir_top_st:fir_top_st_component|ram_lut:Ur2_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_6m41:auto_generated|q_b[0]~Iporta_datain_reg11 ; fir_top:inst1|fir_top_st:fir_top_st_component|ram_lut:Ur2_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_6m41:auto_generated|q_b[0]~Iporta_memory_reg11 ; fir_clock  ; fir_clock ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.56 MHz ( period = 3.913 ns )                           ; fir_top:inst1|fir_top_st:fir_top_st_component|ram_lut:Ur2_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_6m41:auto_generated|q_b[0]~Iporta_datain_reg10 ; fir_top:inst1|fir_top_st:fir_top_st_component|ram_lut:Ur2_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_6m41:auto_generated|q_b[0]~Iporta_memory_reg10 ; fir_clock  ; fir_clock ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.56 MHz ( period = 3.913 ns )                           ; fir_top:inst1|fir_top_st:fir_top_st_component|ram_lut:Ur2_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_6m41:auto_generated|q_b[0]~Iporta_datain_reg9  ; fir_top:inst1|fir_top_st:fir_top_st_component|ram_lut:Ur2_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_6m41:auto_generated|q_b[0]~Iporta_memory_reg9  ; fir_clock  ; fir_clock ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.56 MHz ( period = 3.913 ns )                           ; fir_top:inst1|fir_top_st:fir_top_st_component|ram_lut:Ur2_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_6m41:auto_generated|q_b[0]~Iporta_datain_reg8  ; fir_top:inst1|fir_top_st:fir_top_st_component|ram_lut:Ur2_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_6m41:auto_generated|q_b[0]~Iporta_memory_reg8  ; fir_clock  ; fir_clock ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.56 MHz ( period = 3.913 ns )                           ; fir_top:inst1|fir_top_st:fir_top_st_component|ram_lut:Ur2_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_6m41:auto_generated|q_b[0]~Iporta_datain_reg7  ; fir_top:inst1|fir_top_st:fir_top_st_component|ram_lut:Ur2_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_6m41:auto_generated|q_b[0]~Iporta_memory_reg7  ; fir_clock  ; fir_clock ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.56 MHz ( period = 3.913 ns )                           ; fir_top:inst1|fir_top_st:fir_top_st_component|ram_lut:Ur2_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_6m41:auto_generated|q_b[0]~Iporta_datain_reg6  ; fir_top:inst1|fir_top_st:fir_top_st_component|ram_lut:Ur2_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_6m41:auto_generated|q_b[0]~Iporta_memory_reg6  ; fir_clock  ; fir_clock ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.56 MHz ( period = 3.913 ns )                           ; fir_top:inst1|fir_top_st:fir_top_st_component|ram_lut:Ur2_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_6m41:auto_generated|q_b[0]~Iporta_datain_reg5  ; fir_top:inst1|fir_top_st:fir_top_st_component|ram_lut:Ur2_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_6m41:auto_generated|q_b[0]~Iporta_memory_reg5  ; fir_clock  ; fir_clock ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.56 MHz ( period = 3.913 ns )                           ; fir_top:inst1|fir_top_st:fir_top_st_component|ram_lut:Ur2_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_6m41:auto_generated|q_b[0]~Iporta_datain_reg4  ; fir_top:inst1|fir_top_st:fir_top_st_component|ram_lut:Ur2_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_6m41:auto_generated|q_b[0]~Iporta_memory_reg4  ; fir_clock  ; fir_clock ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.56 MHz ( period = 3.913 ns )                           ; fir_top:inst1|fir_top_st:fir_top_st_component|ram_lut:Ur2_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_6m41:auto_generated|q_b[0]~Iporta_datain_reg3  ; fir_top:inst1|fir_top_st:fir_top_st_component|ram_lut:Ur2_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_6m41:auto_generated|q_b[0]~Iporta_memory_reg3  ; fir_clock  ; fir_clock ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.56 MHz ( period = 3.913 ns )                           ; fir_top:inst1|fir_top_st:fir_top_st_component|ram_lut:Ur2_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_6m41:auto_generated|q_b[0]~Iporta_datain_reg2  ; fir_top:inst1|fir_top_st:fir_top_st_component|ram_lut:Ur2_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_6m41:auto_generated|q_b[0]~Iporta_memory_reg2  ; fir_clock  ; fir_clock ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.56 MHz ( period = 3.913 ns )                           ; fir_top:inst1|fir_top_st:fir_top_st_component|ram_lut:Ur2_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_6m41:auto_generated|q_b[0]~Iporta_datain_reg1  ; fir_top:inst1|fir_top_st:fir_top_st_component|ram_lut:Ur2_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_6m41:auto_generated|q_b[0]~Iporta_memory_reg1  ; fir_clock  ; fir_clock ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.56 MHz ( period = 3.913 ns )                           ; fir_top:inst1|fir_top_st:fir_top_st_component|ram_lut:Ur2_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_6m41:auto_generated|q_b[0]~Iporta_datain_reg0  ; fir_top:inst1|fir_top_st:fir_top_st_component|ram_lut:Ur2_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_6m41:auto_generated|q_b[0]~Iporta_memory_reg0  ; fir_clock  ; fir_clock ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.56 MHz ( period = 3.913 ns )                           ; fir_top:inst1|fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_qs41:auto_generated|q_b[0]~Iporta_datain_reg12 ; fir_top:inst1|fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_qs41:auto_generated|q_b[0]~Iporta_memory_reg12 ; fir_clock  ; fir_clock ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.56 MHz ( period = 3.913 ns )                           ; fir_top:inst1|fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_qs41:auto_generated|q_b[0]~Iporta_datain_reg11 ; fir_top:inst1|fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_qs41:auto_generated|q_b[0]~Iporta_memory_reg11 ; fir_clock  ; fir_clock ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.56 MHz ( period = 3.913 ns )                           ; fir_top:inst1|fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_qs41:auto_generated|q_b[0]~Iporta_datain_reg10 ; fir_top:inst1|fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_qs41:auto_generated|q_b[0]~Iporta_memory_reg10 ; fir_clock  ; fir_clock ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.56 MHz ( period = 3.913 ns )                           ; fir_top:inst1|fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_qs41:auto_generated|q_b[0]~Iporta_datain_reg9  ; fir_top:inst1|fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_qs41:auto_generated|q_b[0]~Iporta_memory_reg9  ; fir_clock  ; fir_clock ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.56 MHz ( period = 3.913 ns )                           ; fir_top:inst1|fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_qs41:auto_generated|q_b[0]~Iporta_datain_reg8  ; fir_top:inst1|fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_qs41:auto_generated|q_b[0]~Iporta_memory_reg8  ; fir_clock  ; fir_clock ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.56 MHz ( period = 3.913 ns )                           ; fir_top:inst1|fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_qs41:auto_generated|q_b[0]~Iporta_datain_reg7  ; fir_top:inst1|fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_qs41:auto_generated|q_b[0]~Iporta_memory_reg7  ; fir_clock  ; fir_clock ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.56 MHz ( period = 3.913 ns )                           ; fir_top:inst1|fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_qs41:auto_generated|q_b[0]~Iporta_datain_reg6  ; fir_top:inst1|fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_qs41:auto_generated|q_b[0]~Iporta_memory_reg6  ; fir_clock  ; fir_clock ; None                        ; None                      ; None                    ;
; N/A                                     ; 255.56 MHz ( period = 3.913 ns )                           ; fir_top:inst1|fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_qs41:auto_generated|q_b[0]~Iporta_datain_reg5  ; fir_top:inst1|fir_top_st:fir_top_st_component|ram_lut:Ur0_n|ram_2pt_var:ram|altsyncram:altsyncram_component|altsyncram_qs41:auto_generated|q_b[0]~Iporta_memory_reg5  ; fir_clock  ; fir_clock ; None                        ; None                      ; None                    ;