my_dqs.v

altera FPGA/CPLD高级篇(VHDL源代码)

// megafunction wizard: %ALTDQS%CBX%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altdqs 

// ============================================================
// File Name: MY_DQS.v
// Megafunction Name(s):
// 			altdqs
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 4.1 Build 207 08/26/2004 SP 1 SJ Full Version
// ************************************************************


//Copyright (C) 1991-2004 Altera Corporation
//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
//support information,  device programming or simulation file,  and any other
//associated  documentation or information  provided by  Altera  or a partner
//under  Altera's   Megafunction   Partnership   Program  may  be  used  only
//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
//other  use  of such  megafunction  design,  netlist,  support  information,
//device programming or simulation file,  or any other  related documentation
//or information  is prohibited  for  any  other purpose,  including, but not
//limited to  modification,  reverse engineering,  de-compiling, or use  with
//any other  silicon devices,  unless such use is  explicitly  licensed under
//a separate agreement with  Altera  or a megafunction partner.  Title to the
//intellectual property,  including patents,  copyrights,  trademarks,  trade
//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
//support  information,  device programming or simulation file,  or any other
//related documentation or information provided by  Altera  or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.


//altdqs DEVICE_FAMILY="STRATIX" dll_delay_chain_length=12 dll_phase_shift="90" dqs_oe_async_reset="none" dqs_oe_power_up="low" dqs_oe_register_mode="register" dqs_oe_sync_reset="none" dqs_output_async_reset="none" dqs_output_power_up="low" dqs_output_sync_reset="none" extend_oe_disable="true" input_frequency="6666ps" number_of_dqs=1 sim_invalid_lock=10000 sim_valid_lock=1 tie_off_dqs_oe_clock_enable="false" tie_off_dqs_output_clock_enable="false" dqinclk dqs_datain_h dqs_datain_l dqs_padio dqsundelayedout inclk oe outclk outclkena
//VERSION_BEGIN 4.1 cbx_altdqs 2004:06:03:10:29:50:SJ cbx_cycloneii 2004:05:18:11:27:16:SJ cbx_mgl 2004:06:17:17:30:06:SJ cbx_stratix 2004:04:28:15:20:14:SJ cbx_stratixii 2004:05:18:11:28:28:SJ  VERSION_END

//synthesis_resources = stratix_dll 1 stratix_io 1 
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module  MY_DQS_adqs_obi1
	( 
	dqinclk,
	dqs_datain_h,
	dqs_datain_l,
	dqs_padio,
	dqsundelayedout,
	inclk,
	oe,
	outclk,
	outclkena) /* synthesis synthesis_clearbox=1 */;
	output   [0:0]  dqinclk;
	input   [0:0]  dqs_datain_h;
	input   [0:0]  dqs_datain_l;
	inout   [0:0]  dqs_padio;
	output   [0:0]  dqsundelayedout;
	input   inclk;
	input   oe;
	input   outclk;
	input   outclkena;

	wire  wire_strx_dll1_delayctrlout;
	wire  wire_strx_io2_combout;
	wire  wire_strx_io2_dqsundelayedout;
	wire  delay_ctrl;

	stratix_dll   strx_dll1
	( 
	.clk(inclk),
	.delayctrlout(wire_strx_dll1_delayctrlout));
	defparam
		strx_dll1.input_frequency = "6666ps",
		strx_dll1.phase_shift = "90",
		strx_dll1.sim_invalid_lock = 10000,
		strx_dll1.sim_valid_lock = 1,
		strx_dll1.lpm_type = "stratix_dll";
	stratix_io   strx_io2
	( 
	.combout(wire_strx_io2_combout),
	.datain(dqs_datain_h[0:0]),
	.ddiodatain(dqs_datain_l[0:0]),
	.ddioregout(),
	.delayctrlin(delay_ctrl),
	.dqsundelayedout(wire_strx_io2_dqsundelayedout),
	.oe(oe),
	.outclk(outclk),
	.outclkena(outclkena),
	.padio(dqs_padio[0:0]),
	.regout()
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.areset(1'b0),
	.inclk(1'b0),
	.inclkena(1'b1),
	.sreset(1'b0)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.devclrn(),
	.devoe(),
	.devpor()
	// synopsys translate_on
	);
	defparam
		strx_io2.ddio_mode = "output",
		strx_io2.extend_oe_disable = "true",
		strx_io2.oe_async_reset = "none",
		strx_io2.oe_power_up = "low",
		strx_io2.oe_register_mode = "register",
		strx_io2.oe_sync_reset = "none",
		strx_io2.open_drain_output = "false",
		strx_io2.operation_mode = "bidir",
		strx_io2.output_async_reset = "none",
		strx_io2.output_power_up = "low",
		strx_io2.output_register_mode = "register",
		strx_io2.output_sync_reset = "none",
		strx_io2.sim_dll_phase_shift = "90",
		strx_io2.sim_dqs_input_frequency = "6666ps",
		strx_io2.tie_off_oe_clock_enable = "false",
		strx_io2.tie_off_output_clock_enable = "false",
		strx_io2.lpm_type = "stratix_io";
	assign
		delay_ctrl = wire_strx_dll1_delayctrlout,
		dqinclk = {wire_strx_io2_combout},
		dqsundelayedout = {wire_strx_io2_dqsundelayedout};
endmodule //MY_DQS_adqs_obi1
//VALID FILE


// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module MY_DQS (
	outclk,
	oe,
	dqs_datain_h,
	inclk,
	dqs_datain_l,
	dqs_padio,
	dqinclk,
	dqsundelayedout)/* synthesis synthesis_clearbox = 1 */;

	input	  outclk;
	input	  oe;
	input	[0:0]  dqs_datain_h;
	input	  inclk;
	input	[0:0]  dqs_datain_l;
	inout	[0:0]  dqs_padio;
	output	[0:0]  dqinclk;
	output	[0:0]  dqsundelayedout;

	wire [0:0] sub_wire0;
	wire [0:0] sub_wire1;
	wire  sub_wire2 = 1'h1;
	wire [0:0] dqinclk = sub_wire0[0:0];
	wire [0:0] dqsundelayedout = sub_wire1[0:0];

	MY_DQS_adqs_obi1	MY_DQS_adqs_obi1_component (
				.dqs_padio (dqs_padio),
				.outclk (outclk),
				.oe (oe),
				.dqs_datain_h (dqs_datain_h),
				.outclkena (sub_wire2),
				.inclk (inclk),
				.dqs_datain_l (dqs_datain_l),
				.dqinclk (sub_wire0),
				.dqsundelayedout (sub_wire1));

endmodule

// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ALTDQS_INPUT_FREQUENCY_COMBO STRING "150"
// Retrieval info: PRIVATE: ALTDQS_SIM_VALID_LOCK_EDIT STRING "1"
// Retrieval info: PRIVATE: ALTDQS_OE_REGISTER_MODE_CHECK STRING "1"
// Retrieval info: PRIVATE: DLL_STATIC_OFFSET NUMERIC "0"
// Retrieval info: PRIVATE: OE_ASYNC_RESET NUMERIC "2"
// Retrieval info: PRIVATE: DLL_DELAY_CHAIN_LENGTH NUMERIC "12"
// Retrieval info: PRIVATE: DLL_OFFSETCTRL_MODE NUMERIC "3"
// Retrieval info: PRIVATE: JITTER_REDUCTION_CHECK STRING "0"
// Retrieval info: PRIVATE: DQSB_MODE NUMERIC "0"
// Retrieval info: PRIVATE: OE_POWER_UP_HIGH STRING "0"
// Retrieval info: PRIVATE: DLL_DELAYCTRL_MODE NUMERIC "0"
// Retrieval info: PRIVATE: CYCLONEII_INPUT_FREQUENCY_UNIT STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix"
// Retrieval info: PRIVATE: IDEAL_PHASE_SHIFT STRING "90.00"
// Retrieval info: PRIVATE: ALTDQS_SIM_INVALID_LOCK_EDIT STRING "10000"
// Retrieval info: PRIVATE: ALTDQS_CREATE_OE_CHECK STRING "1"
// Retrieval info: PRIVATE: GATED_DQS NUMERIC "0"
// Retrieval info: PRIVATE: CYCLONEII_DELAY_IN_PS_UNIT STRING "ps"
// Retrieval info: PRIVATE: PREV_DLL_OFFSETCTRL_MODE NUMERIC "0"
// Retrieval info: PRIVATE: ALTDQS_EXTEND_OE_DISABLE_CHECK STRING "1"
// Retrieval info: PRIVATE: DLL_PHASE_SHIFT STRING "90"
// Retrieval info: PRIVATE: DELAY_BUFFER_MODE STRING "0"
// Retrieval info: PRIVATE: ALTDQS_NUMBER_OF_DQS_COMBO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_POWER_UP_HIGH STRING "0"
// Retrieval info: PRIVATE: OUTPUT_ASYNC_RESET NUMERIC "2"
// Retrieval info: PRIVATE: CTRL_LATCHES_ENABLE_CHECK STRING "1"
// Retrieval info: PRIVATE: OE_SYNC_RESET NUMERIC "2"
// Retrieval info: PRIVATE: ALTDQS_INPUT_FREQUENCY_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: FREQUENCY_MODE NUMERIC "0"
// Retrieval info: PRIVATE: CYCLONEII_INPUT_FREQUENCY STRING "133.332"
// Retrieval info: PRIVATE: EDGE_DETECT_ENABLE_CHECK STRING "0"
// Retrieval info: PRIVATE: OUTPUT_SYNC_RESET NUMERIC "2"
// Retrieval info: CONSTANT: DQS_OE_ASYNC_RESET STRING "NONE"
// Retrieval info: CONSTANT: TIE_OFF_DQS_OUTPUT_CLOCK_ENABLE STRING "FALSE"
// Retrieval info: CONSTANT: DQS_OUTPUT_POWER_UP STRING "LOW"
// Retrieval info: CONSTANT: SIM_INVALID_LOCK NUMERIC "10000"
// Retrieval info: CONSTANT: DQS_OE_REGISTER_MODE STRING "REGISTER"
// Retrieval info: CONSTANT: DQS_OE_POWER_UP STRING "LOW"
// Retrieval info: CONSTANT: DQS_OUTPUT_ASYNC_RESET STRING "NONE"
// Retrieval info: CONSTANT: DLL_DELAY_CHAIN_LENGTH NUMERIC "12"
// Retrieval info: CONSTANT: TIE_OFF_DQS_OE_CLOCK_ENABLE STRING "FALSE"
// Retrieval info: CONSTANT: SIM_VALID_LOCK NUMERIC "1"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix"
// Retrieval info: CONSTANT: DQS_OE_SYNC_RESET STRING "NONE"
// Retrieval info: CONSTANT: NUMBER_OF_DQS NUMERIC "1"
// Retrieval info: CONSTANT: DLL_PHASE_SHIFT STRING "90"
// Retrieval info: CONSTANT: DQS_OUTPUT_SYNC_RESET STRING "NONE"
// Retrieval info: CONSTANT: INPUT_FREQUENCY STRING "6666ps"
// Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "TRUE"
// Retrieval info: USED_PORT: outclk 0 0 0 0 INPUT NODEFVAL "outclk"
// Retrieval info: USED_PORT: dqs_padio 0 0 1 0 BIDIR NODEFVAL "dqs_padio[0..0]"
// Retrieval info: USED_PORT: oe 0 0 0 0 INPUT NODEFVAL "oe"
// Retrieval info: USED_PORT: dqs_datain_h 0 0 1 0 INPUT NODEFVAL "dqs_datain_h[0..0]"
// Retrieval info: USED_PORT: inclk 0 0 0 0 INPUT NODEFVAL "inclk"
// Retrieval info: USED_PORT: dqs_datain_l 0 0 1 0 INPUT NODEFVAL "dqs_datain_l[0..0]"
// Retrieval info: USED_PORT: dqinclk 0 0 1 0 OUTPUT NODEFVAL "dqinclk[0..0]"
// Retrieval info: USED_PORT: dqsundelayedout 0 0 1 0 OUTPUT NODEFVAL "dqsundelayedout[0..0]"
// Retrieval info: CONNECT: @outclkena 0 0 0 0 VCC 0 0 0 0
// Retrieval info: CONNECT: @dqs_datain_h 0 0 1 0 dqs_datain_h 0 0 1 0
// Retrieval info: CONNECT: @inclk 0 0 0 0 inclk 0 0 0 0
// Retrieval info: CONNECT: @oe 0 0 0 0 oe 0 0 0 0
// Retrieval info: CONNECT: @outclk 0 0 0 0 outclk 0 0 0 0
// Retrieval info: CONNECT: dqsundelayedout 0 0 1 0 @dqsundelayedout 0 0 1 0
// Retrieval info: CONNECT: @dqs_datain_l 0 0 1 0 dqs_datain_l 0 0 1 0
// Retrieval info: CONNECT: dqs_padio 0 0 1 0 @dqs_padio 0 0 1 0
// Retrieval info: CONNECT: dqinclk 0 0 1 0 @dqinclk 0 0 1 0
// Retrieval info: GEN_FILE: TYPE_NORMAL MY_DQS.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL MY_DQS.inc FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL MY_DQS.cmp FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL MY_DQS.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL MY_DQS_inst.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL MY_DQS_bb.v TRUE FALSE