my_dq.v

altera FPGA/CPLD高级篇(VHDL源代码)

	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.areset(1'b0),
	.delayctrlin(1'b0),
	.inclkena(1'b1),
	.outclkena(1'b1),
	.sreset(1'b0)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.devclrn(),
	.devoe(),
	.devpor()
	// synopsys translate_on
	);
	defparam
		dq_ioa_4.ddio_mode = "bidir",
		dq_ioa_4.extend_oe_disable = "false",
		dq_ioa_4.input_async_reset = "none",
		dq_ioa_4.input_power_up = "low",
		dq_ioa_4.input_register_mode = "register",
		dq_ioa_4.oe_async_reset = "none",
		dq_ioa_4.oe_power_up = "low",
		dq_ioa_4.oe_register_mode = "register",
		dq_ioa_4.operation_mode = "bidir",
		dq_ioa_4.output_async_reset = "none",
		dq_ioa_4.output_power_up = "low",
		dq_ioa_4.output_register_mode = "register",
		dq_ioa_4.lpm_type = "stratix_io";
	stratix_io   dq_ioa_5
	( 
	.combout(),
	.datain(wire_dq_ioa_datain[5:5]),
	.ddiodatain(wire_dq_ioa_ddiodatain[5:5]),
	.ddioregout(wire_dq_ioa_ddioregout[5:5]),
	.dqsundelayedout(),
	.inclk((~ inclock)),
	.oe(oe),
	.outclk(outclock),
	.padio(padio[5:5]),
	.regout(wire_dq_ioa_regout[5:5])
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.areset(1'b0),
	.delayctrlin(1'b0),
	.inclkena(1'b1),
	.outclkena(1'b1),
	.sreset(1'b0)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.devclrn(),
	.devoe(),
	.devpor()
	// synopsys translate_on
	);
	defparam
		dq_ioa_5.ddio_mode = "bidir",
		dq_ioa_5.extend_oe_disable = "false",
		dq_ioa_5.input_async_reset = "none",
		dq_ioa_5.input_power_up = "low",
		dq_ioa_5.input_register_mode = "register",
		dq_ioa_5.oe_async_reset = "none",
		dq_ioa_5.oe_power_up = "low",
		dq_ioa_5.oe_register_mode = "register",
		dq_ioa_5.operation_mode = "bidir",
		dq_ioa_5.output_async_reset = "none",
		dq_ioa_5.output_power_up = "low",
		dq_ioa_5.output_register_mode = "register",
		dq_ioa_5.lpm_type = "stratix_io";
	stratix_io   dq_ioa_6
	( 
	.combout(),
	.datain(wire_dq_ioa_datain[6:6]),
	.ddiodatain(wire_dq_ioa_ddiodatain[6:6]),
	.ddioregout(wire_dq_ioa_ddioregout[6:6]),
	.dqsundelayedout(),
	.inclk((~ inclock)),
	.oe(oe),
	.outclk(outclock),
	.padio(padio[6:6]),
	.regout(wire_dq_ioa_regout[6:6])
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.areset(1'b0),
	.delayctrlin(1'b0),
	.inclkena(1'b1),
	.outclkena(1'b1),
	.sreset(1'b0)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.devclrn(),
	.devoe(),
	.devpor()
	// synopsys translate_on
	);
	defparam
		dq_ioa_6.ddio_mode = "bidir",
		dq_ioa_6.extend_oe_disable = "false",
		dq_ioa_6.input_async_reset = "none",
		dq_ioa_6.input_power_up = "low",
		dq_ioa_6.input_register_mode = "register",
		dq_ioa_6.oe_async_reset = "none",
		dq_ioa_6.oe_power_up = "low",
		dq_ioa_6.oe_register_mode = "register",
		dq_ioa_6.operation_mode = "bidir",
		dq_ioa_6.output_async_reset = "none",
		dq_ioa_6.output_power_up = "low",
		dq_ioa_6.output_register_mode = "register",
		dq_ioa_6.lpm_type = "stratix_io";
	stratix_io   dq_ioa_7
	( 
	.combout(),
	.datain(wire_dq_ioa_datain[7:7]),
	.ddiodatain(wire_dq_ioa_ddiodatain[7:7]),
	.ddioregout(wire_dq_ioa_ddioregout[7:7]),
	.dqsundelayedout(),
	.inclk((~ inclock)),
	.oe(oe),
	.outclk(outclock),
	.padio(padio[7:7]),
	.regout(wire_dq_ioa_regout[7:7])
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.areset(1'b0),
	.delayctrlin(1'b0),
	.inclkena(1'b1),
	.outclkena(1'b1),
	.sreset(1'b0)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.devclrn(),
	.devoe(),
	.devpor()
	// synopsys translate_on
	);
	defparam
		dq_ioa_7.ddio_mode = "bidir",
		dq_ioa_7.extend_oe_disable = "false",
		dq_ioa_7.input_async_reset = "none",
		dq_ioa_7.input_power_up = "low",
		dq_ioa_7.input_register_mode = "register",
		dq_ioa_7.oe_async_reset = "none",
		dq_ioa_7.oe_power_up = "low",
		dq_ioa_7.oe_register_mode = "register",
		dq_ioa_7.operation_mode = "bidir",
		dq_ioa_7.output_async_reset = "none",
		dq_ioa_7.output_power_up = "low",
		dq_ioa_7.output_register_mode = "register",
		dq_ioa_7.lpm_type = "stratix_io";
	assign
		wire_dq_ioa_datain = datain_h,
		wire_dq_ioa_ddiodatain = datain_l;
	assign
		dataout_h = wire_dq_ioa_regout,
		dataout_l = wire_dq_ioa_ddioregout;
endmodule //MY_DQ_dq_4rg
//VALID FILE


// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module MY_DQ (
	datain_h,
	datain_l,
	inclock,
	outclock,
	oe,
	dataout_h,
	dataout_l,
	padio)/* synthesis synthesis_clearbox = 1 */;

	input	[7:0]  datain_h;
	input	[7:0]  datain_l;
	input	  inclock;
	input	  outclock;
	input	  oe;
	output	[7:0]  dataout_h;
	output	[7:0]  dataout_l;
	inout	[7:0]  padio;

	wire [7:0] sub_wire0;
	wire [7:0] sub_wire1;
	wire [7:0] dataout_h = sub_wire0[7:0];
	wire [7:0] dataout_l = sub_wire1[7:0];

	MY_DQ_dq_4rg	MY_DQ_dq_4rg_component (
				.padio (padio),
				.outclock (outclock),
				.inclock (inclock),
				.oe (oe),
				.datain_h (datain_h),
				.datain_l (datain_l),
				.dataout_h (sub_wire0),
				.dataout_l (sub_wire1));

endmodule

// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: WIDTH NUMERIC "8"
// Retrieval info: PRIVATE: ARESET_MODE NUMERIC "2"
// Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix"
// Retrieval info: PRIVATE: CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: OE NUMERIC "1"
// Retrieval info: PRIVATE: OE_REG NUMERIC "1"
// Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0"
// Retrieval info: PRIVATE: USE_SEC_CLOCK NUMERIC "0"
// Retrieval info: CONSTANT: NUMBER_OF_DQ NUMERIC "8"
// Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix"
// Retrieval info: CONSTANT: OE_REG STRING "REGISTERED"
// Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altdq"
// Retrieval info: CONSTANT: DDIOINCLK_INPUT STRING "NEGATED_INCLK"
// Retrieval info: USED_PORT: datain_h 0 0 8 0 INPUT NODEFVAL datain_h[7..0]
// Retrieval info: USED_PORT: datain_l 0 0 8 0 INPUT NODEFVAL datain_l[7..0]
// Retrieval info: USED_PORT: dataout_h 0 0 8 0 OUTPUT NODEFVAL dataout_h[7..0]
// Retrieval info: USED_PORT: dataout_l 0 0 8 0 OUTPUT NODEFVAL dataout_l[7..0]
// Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT NODEFVAL inclock
// Retrieval info: USED_PORT: padio 0 0 8 0 BIDIR NODEFVAL padio[7..0]
// Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT NODEFVAL outclock
// Retrieval info: USED_PORT: oe 0 0 0 0 INPUT VCC oe
// Retrieval info: CONNECT: @datain_h 0 0 8 0 datain_h 0 0 8 0
// Retrieval info: CONNECT: @datain_l 0 0 8 0 datain_l 0 0 8 0
// Retrieval info: CONNECT: dataout_h 0 0 8 0 @dataout_h 0 0 8 0
// Retrieval info: CONNECT: dataout_l 0 0 8 0 @dataout_l 0 0 8 0
// Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0
// Retrieval info: CONNECT: padio 0 0 8 0 @padio 0 0 8 0
// Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
// Retrieval info: CONNECT: @oe 0 0 0 0 oe 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL MY_DQ.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL MY_DQ.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL MY_DQ.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL MY_DQ.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL MY_DQ_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL MY_DQ_bb.v TRUE