my_dq_bb.v

altera FPGA/CPLD高级篇(VHDL源代码)

// megafunction wizard: %ALTDQ%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altdq 

// ============================================================
// File Name: MY_DQ.v
// Megafunction Name(s):
// 			altdq
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 4.1 Build 207 08/26/2004 SP 1.04 SJ Full Version
// ************************************************************

//Copyright (C) 1991-2004 Altera Corporation
//Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
//support information,  device programming or simulation file,  and any other
//associated  documentation or information  provided by  Altera  or a partner
//under  Altera's   Megafunction   Partnership   Program  may  be  used  only
//to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
//other  use  of such  megafunction  design,  netlist,  support  information,
//device programming or simulation file,  or any other  related documentation
//or information  is prohibited  for  any  other purpose,  including, but not
//limited to  modification,  reverse engineering,  de-compiling, or use  with
//any other  silicon devices,  unless such use is  explicitly  licensed under
//a separate agreement with  Altera  or a megafunction partner.  Title to the
//intellectual property,  including patents,  copyrights,  trademarks,  trade
//secrets,  or maskworks,  embodied in any such megafunction design, netlist,
//support  information,  device programming or simulation file,  or any other
//related documentation or information provided by  Altera  or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.

module MY_DQ (
	datain_h,
	datain_l,
	inclock,
	outclock,
	oe,
	dataout_h,
	dataout_l,
	padio)/* synthesis synthesis_clearbox = 1 */;

	input	[7:0]  datain_h;
	input	[7:0]  datain_l;
	input	  inclock;
	input	  outclock;
	input	  oe;
	output	[7:0]  dataout_h;
	output	[7:0]  dataout_l;
	inout	[7:0]  padio;

endmodule

// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: WIDTH NUMERIC "8"
// Retrieval info: PRIVATE: ARESET_MODE NUMERIC "2"
// Retrieval info: PRIVATE: POWER_UP_HIGH NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix"
// Retrieval info: PRIVATE: CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: OE NUMERIC "1"
// Retrieval info: PRIVATE: OE_REG NUMERIC "1"
// Retrieval info: PRIVATE: EXTEND_OE_DISABLE NUMERIC "0"
// Retrieval info: PRIVATE: USE_SEC_CLOCK NUMERIC "0"
// Retrieval info: CONSTANT: NUMBER_OF_DQ NUMERIC "8"
// Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix"
// Retrieval info: CONSTANT: OE_REG STRING "REGISTERED"
// Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altdq"
// Retrieval info: CONSTANT: DDIOINCLK_INPUT STRING "NEGATED_INCLK"
// Retrieval info: USED_PORT: datain_h 0 0 8 0 INPUT NODEFVAL datain_h[7..0]
// Retrieval info: USED_PORT: datain_l 0 0 8 0 INPUT NODEFVAL datain_l[7..0]
// Retrieval info: USED_PORT: dataout_h 0 0 8 0 OUTPUT NODEFVAL dataout_h[7..0]
// Retrieval info: USED_PORT: dataout_l 0 0 8 0 OUTPUT NODEFVAL dataout_l[7..0]
// Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT NODEFVAL inclock
// Retrieval info: USED_PORT: padio 0 0 8 0 BIDIR NODEFVAL padio[7..0]
// Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT NODEFVAL outclock
// Retrieval info: USED_PORT: oe 0 0 0 0 INPUT VCC oe
// Retrieval info: CONNECT: @datain_h 0 0 8 0 datain_h 0 0 8 0
// Retrieval info: CONNECT: @datain_l 0 0 8 0 datain_l 0 0 8 0
// Retrieval info: CONNECT: dataout_h 0 0 8 0 @dataout_h 0 0 8 0
// Retrieval info: CONNECT: dataout_l 0 0 8 0 @dataout_l 0 0 8 0
// Retrieval info: CONNECT: @inclock 0 0 0 0 inclock 0 0 0 0
// Retrieval info: CONNECT: padio 0 0 8 0 @padio 0 0 8 0
// Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
// Retrieval info: CONNECT: @oe 0 0 0 0 oe 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL MY_DQ.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL MY_DQ.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL MY_DQ.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL MY_DQ.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL MY_DQ_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL MY_DQ_bb.v TRUE