datapath.bdf

altera FPGA/CPLD高级篇(VHDL源代码)

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	(port
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(text "To internal logic" (rect 1120 320 1208 334)(font "Arial" (font_size 8)))
(text "To internal logic" (rect 1120 416 1208 430)(font "Arial" (font_size 8)))
(text "From internal logic" (rect 192 112 294 126)(font "Arial" (font_size 8)))
(text "From internal logic" (rect 208 328 310 342)(font "Arial" (font_size 8)))
(text "From internal logic" (rect 208 416 310 430)(font "Arial" (font_size 8)))
(text "Reference Clock" (rect 416 72 510 86)(font "Arial" (font_size 8)))