plb_bram_if_cntlr_1_bram_elaborate.v

基于Xilinx-XUPV2P开发平台的嵌入式系统实验例程：实验4编写基本的应用程序

  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_14 is WRITE_FIRST;


  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_15 is "WRITE_FIRST";
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_15 is "WRITE_FIRST";
  RAMB16_S2_S2
    ramb16_s2_s2_15 (
      .ADDRA ( BRAM_Addr_A[16:28] ),
      .CLKA ( BRAM_Clk_A ),
      .DIA ( dina[33:32] ),
      .DOA ( douta[33:32] ),
      .ENA ( BRAM_EN_A ),
      .SSRA ( BRAM_Rst_A ),
      .WEA ( BRAM_WEN_A[3] ),
      .ADDRB ( BRAM_Addr_B[16:28] ),
      .CLKB ( BRAM_Clk_B ),
      .DIB ( dinb[33:32] ),
      .DOB ( doutb[33:32] ),
      .ENB ( BRAM_EN_B ),
      .SSRB ( BRAM_Rst_B ),
      .WEB ( BRAM_WEN_B[3] )
    );
  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_15 is WRITE_FIRST;
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_15 is WRITE_FIRST;


  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_16 is "WRITE_FIRST";
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_16 is "WRITE_FIRST";
  RAMB16_S2_S2
    ramb16_s2_s2_16 (
      .ADDRA ( BRAM_Addr_A[16:28] ),
      .CLKA ( BRAM_Clk_A ),
      .DIA ( dina[31:30] ),
      .DOA ( douta[31:30] ),
      .ENA ( BRAM_EN_A ),
      .SSRA ( BRAM_Rst_A ),
      .WEA ( BRAM_WEN_A[4] ),
      .ADDRB ( BRAM_Addr_B[16:28] ),
      .CLKB ( BRAM_Clk_B ),
      .DIB ( dinb[31:30] ),
      .DOB ( doutb[31:30] ),
      .ENB ( BRAM_EN_B ),
      .SSRB ( BRAM_Rst_B ),
      .WEB ( BRAM_WEN_B[4] )
    );
  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_16 is WRITE_FIRST;
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_16 is WRITE_FIRST;


  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_17 is "WRITE_FIRST";
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_17 is "WRITE_FIRST";
  RAMB16_S2_S2
    ramb16_s2_s2_17 (
      .ADDRA ( BRAM_Addr_A[16:28] ),
      .CLKA ( BRAM_Clk_A ),
      .DIA ( dina[29:28] ),
      .DOA ( douta[29:28] ),
      .ENA ( BRAM_EN_A ),
      .SSRA ( BRAM_Rst_A ),
      .WEA ( BRAM_WEN_A[4] ),
      .ADDRB ( BRAM_Addr_B[16:28] ),
      .CLKB ( BRAM_Clk_B ),
      .DIB ( dinb[29:28] ),
      .DOB ( doutb[29:28] ),
      .ENB ( BRAM_EN_B ),
      .SSRB ( BRAM_Rst_B ),
      .WEB ( BRAM_WEN_B[4] )
    );
  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_17 is WRITE_FIRST;
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_17 is WRITE_FIRST;


  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_18 is "WRITE_FIRST";
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_18 is "WRITE_FIRST";
  RAMB16_S2_S2
    ramb16_s2_s2_18 (
      .ADDRA ( BRAM_Addr_A[16:28] ),
      .CLKA ( BRAM_Clk_A ),
      .DIA ( dina[27:26] ),
      .DOA ( douta[27:26] ),
      .ENA ( BRAM_EN_A ),
      .SSRA ( BRAM_Rst_A ),
      .WEA ( BRAM_WEN_A[4] ),
      .ADDRB ( BRAM_Addr_B[16:28] ),
      .CLKB ( BRAM_Clk_B ),
      .DIB ( dinb[27:26] ),
      .DOB ( doutb[27:26] ),
      .ENB ( BRAM_EN_B ),
      .SSRB ( BRAM_Rst_B ),
      .WEB ( BRAM_WEN_B[4] )
    );
  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_18 is WRITE_FIRST;
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_18 is WRITE_FIRST;


  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_19 is "WRITE_FIRST";
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_19 is "WRITE_FIRST";
  RAMB16_S2_S2
    ramb16_s2_s2_19 (
      .ADDRA ( BRAM_Addr_A[16:28] ),
      .CLKA ( BRAM_Clk_A ),
      .DIA ( dina[25:24] ),
      .DOA ( douta[25:24] ),
      .ENA ( BRAM_EN_A ),
      .SSRA ( BRAM_Rst_A ),
      .WEA ( BRAM_WEN_A[4] ),
      .ADDRB ( BRAM_Addr_B[16:28] ),
      .CLKB ( BRAM_Clk_B ),
      .DIB ( dinb[25:24] ),
      .DOB ( doutb[25:24] ),
      .ENB ( BRAM_EN_B ),
      .SSRB ( BRAM_Rst_B ),
      .WEB ( BRAM_WEN_B[4] )
    );
  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_19 is WRITE_FIRST;
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_19 is WRITE_FIRST;


  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_20 is "WRITE_FIRST";
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_20 is "WRITE_FIRST";
  RAMB16_S2_S2
    ramb16_s2_s2_20 (
      .ADDRA ( BRAM_Addr_A[16:28] ),
      .CLKA ( BRAM_Clk_A ),
      .DIA ( dina[23:22] ),
      .DOA ( douta[23:22] ),
      .ENA ( BRAM_EN_A ),
      .SSRA ( BRAM_Rst_A ),
      .WEA ( BRAM_WEN_A[5] ),
      .ADDRB ( BRAM_Addr_B[16:28] ),
      .CLKB ( BRAM_Clk_B ),
      .DIB ( dinb[23:22] ),
      .DOB ( doutb[23:22] ),
      .ENB ( BRAM_EN_B ),
      .SSRB ( BRAM_Rst_B ),
      .WEB ( BRAM_WEN_B[5] )
    );
  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_20 is WRITE_FIRST;
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_20 is WRITE_FIRST;


  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_21 is "WRITE_FIRST";
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_21 is "WRITE_FIRST";
  RAMB16_S2_S2
    ramb16_s2_s2_21 (
      .ADDRA ( BRAM_Addr_A[16:28] ),
      .CLKA ( BRAM_Clk_A ),
      .DIA ( dina[21:20] ),
      .DOA ( douta[21:20] ),
      .ENA ( BRAM_EN_A ),
      .SSRA ( BRAM_Rst_A ),
      .WEA ( BRAM_WEN_A[5] ),
      .ADDRB ( BRAM_Addr_B[16:28] ),
      .CLKB ( BRAM_Clk_B ),
      .DIB ( dinb[21:20] ),
      .DOB ( doutb[21:20] ),
      .ENB ( BRAM_EN_B ),
      .SSRB ( BRAM_Rst_B ),
      .WEB ( BRAM_WEN_B[5] )
    );
  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_21 is WRITE_FIRST;
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_21 is WRITE_FIRST;


  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_22 is "WRITE_FIRST";
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_22 is "WRITE_FIRST";
  RAMB16_S2_S2
    ramb16_s2_s2_22 (
      .ADDRA ( BRAM_Addr_A[16:28] ),
      .CLKA ( BRAM_Clk_A ),
      .DIA ( dina[19:18] ),
      .DOA ( douta[19:18] ),
      .ENA ( BRAM_EN_A ),
      .SSRA ( BRAM_Rst_A ),
      .WEA ( BRAM_WEN_A[5] ),
      .ADDRB ( BRAM_Addr_B[16:28] ),
      .CLKB ( BRAM_Clk_B ),
      .DIB ( dinb[19:18] ),
      .DOB ( doutb[19:18] ),
      .ENB ( BRAM_EN_B ),
      .SSRB ( BRAM_Rst_B ),
      .WEB ( BRAM_WEN_B[5] )
    );
  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_22 is WRITE_FIRST;
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_22 is WRITE_FIRST;


  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_23 is "WRITE_FIRST";
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_23 is "WRITE_FIRST";
  RAMB16_S2_S2
    ramb16_s2_s2_23 (
      .ADDRA ( BRAM_Addr_A[16:28] ),
      .CLKA ( BRAM_Clk_A ),
      .DIA ( dina[17:16] ),
      .DOA ( douta[17:16] ),
      .ENA ( BRAM_EN_A ),
      .SSRA ( BRAM_Rst_A ),
      .WEA ( BRAM_WEN_A[5] ),
      .ADDRB ( BRAM_Addr_B[16:28] ),
      .CLKB ( BRAM_Clk_B ),
      .DIB ( dinb[17:16] ),
      .DOB ( doutb[17:16] ),
      .ENB ( BRAM_EN_B ),
      .SSRB ( BRAM_Rst_B ),
      .WEB ( BRAM_WEN_B[5] )
    );
  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_23 is WRITE_FIRST;
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_23 is WRITE_FIRST;


  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_24 is "WRITE_FIRST";
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_24 is "WRITE_FIRST";
  RAMB16_S2_S2
    ramb16_s2_s2_24 (
      .ADDRA ( BRAM_Addr_A[16:28] ),
      .CLKA ( BRAM_Clk_A ),
      .DIA ( dina[15:14] ),
      .DOA ( douta[15:14] ),
      .ENA ( BRAM_EN_A ),
      .SSRA ( BRAM_Rst_A ),
      .WEA ( BRAM_WEN_A[6] ),
      .ADDRB ( BRAM_Addr_B[16:28] ),
      .CLKB ( BRAM_Clk_B ),
      .DIB ( dinb[15:14] ),
      .DOB ( doutb[15:14] ),
      .ENB ( BRAM_EN_B ),
      .SSRB ( BRAM_Rst_B ),
      .WEB ( BRAM_WEN_B[6] )
    );
  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_24 is WRITE_FIRST;
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_24 is WRITE_FIRST;


  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_25 is "WRITE_FIRST";
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_25 is "WRITE_FIRST";
  RAMB16_S2_S2
    ramb16_s2_s2_25 (
      .ADDRA ( BRAM_Addr_A[16:28] ),
      .CLKA ( BRAM_Clk_A ),
      .DIA ( dina[13:12] ),
      .DOA ( douta[13:12] ),
      .ENA ( BRAM_EN_A ),
      .SSRA ( BRAM_Rst_A ),
      .WEA ( BRAM_WEN_A[6] ),
      .ADDRB ( BRAM_Addr_B[16:28] ),
      .CLKB ( BRAM_Clk_B ),
      .DIB ( dinb[13:12] ),
      .DOB ( doutb[13:12] ),
      .ENB ( BRAM_EN_B ),
      .SSRB ( BRAM_Rst_B ),
      .WEB ( BRAM_WEN_B[6] )
    );
  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_25 is WRITE_FIRST;
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_25 is WRITE_FIRST;


  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_26 is "WRITE_FIRST";
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_26 is "WRITE_FIRST";
  RAMB16_S2_S2
    ramb16_s2_s2_26 (
      .ADDRA ( BRAM_Addr_A[16:28] ),
      .CLKA ( BRAM_Clk_A ),
      .DIA ( dina[11:10] ),
      .DOA ( douta[11:10] ),
      .ENA ( BRAM_EN_A ),
      .SSRA ( BRAM_Rst_A ),
      .WEA ( BRAM_WEN_A[6] ),
      .ADDRB ( BRAM_Addr_B[16:28] ),
      .CLKB ( BRAM_Clk_B ),
      .DIB ( dinb[11:10] ),
      .DOB ( doutb[11:10] ),
      .ENB ( BRAM_EN_B ),
      .SSRB ( BRAM_Rst_B ),
      .WEB ( BRAM_WEN_B[6] )
    );
  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_26 is WRITE_FIRST;
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_26 is WRITE_FIRST;


  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_27 is "WRITE_FIRST";
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_27 is "WRITE_FIRST";
  RAMB16_S2_S2
    ramb16_s2_s2_27 (
      .ADDRA ( BRAM_Addr_A[16:28] ),
      .CLKA ( BRAM_Clk_A ),
      .DIA ( dina[9:8] ),
      .DOA ( douta[9:8] ),
      .ENA ( BRAM_EN_A ),
      .SSRA ( BRAM_Rst_A ),
      .WEA ( BRAM_WEN_A[6] ),
      .ADDRB ( BRAM_Addr_B[16:28] ),
      .CLKB ( BRAM_Clk_B ),
      .DIB ( dinb[9:8] ),
      .DOB ( doutb[9:8] ),
      .ENB ( BRAM_EN_B ),
      .SSRB ( BRAM_Rst_B ),
      .WEB ( BRAM_WEN_B[6] )
    );
  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_27 is WRITE_FIRST;
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_27 is WRITE_FIRST;


  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_28 is "WRITE_FIRST";
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_28 is "WRITE_FIRST";
  RAMB16_S2_S2
    ramb16_s2_s2_28 (
      .ADDRA ( BRAM_Addr_A[16:28] ),
      .CLKA ( BRAM_Clk_A ),
      .DIA ( dina[7:6] ),
      .DOA ( douta[7:6] ),
      .ENA ( BRAM_EN_A ),
      .SSRA ( BRAM_Rst_A ),
      .WEA ( BRAM_WEN_A[7] ),
      .ADDRB ( BRAM_Addr_B[16:28] ),
      .CLKB ( BRAM_Clk_B ),
      .DIB ( dinb[7:6] ),
      .DOB ( doutb[7:6] ),
      .ENB ( BRAM_EN_B ),
      .SSRB ( BRAM_Rst_B ),
      .WEB ( BRAM_WEN_B[7] )
    );
  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_28 is WRITE_FIRST;
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_28 is WRITE_FIRST;


  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_29 is "WRITE_FIRST";
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_29 is "WRITE_FIRST";
  RAMB16_S2_S2
    ramb16_s2_s2_29 (
      .ADDRA ( BRAM_Addr_A[16:28] ),
      .CLKA ( BRAM_Clk_A ),
      .DIA ( dina[5:4] ),
      .DOA ( douta[5:4] ),
      .ENA ( BRAM_EN_A ),
      .SSRA ( BRAM_Rst_A ),
      .WEA ( BRAM_WEN_A[7] ),
      .ADDRB ( BRAM_Addr_B[16:28] ),
      .CLKB ( BRAM_Clk_B ),
      .DIB ( dinb[5:4] ),
      .DOB ( doutb[5:4] ),
      .ENB ( BRAM_EN_B ),
      .SSRB ( BRAM_Rst_B ),
      .WEB ( BRAM_WEN_B[7] )
    );
  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_29 is WRITE_FIRST;
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_29 is WRITE_FIRST;


  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_30 is "WRITE_FIRST";
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_30 is "WRITE_FIRST";
  RAMB16_S2_S2
    ramb16_s2_s2_30 (
      .ADDRA ( BRAM_Addr_A[16:28] ),
      .CLKA ( BRAM_Clk_A ),
      .DIA ( dina[3:2] ),
      .DOA ( douta[3:2] ),
      .ENA ( BRAM_EN_A ),
      .SSRA ( BRAM_Rst_A ),
      .WEA ( BRAM_WEN_A[7] ),
      .ADDRB ( BRAM_Addr_B[16:28] ),
      .CLKB ( BRAM_Clk_B ),
      .DIB ( dinb[3:2] ),
      .DOB ( doutb[3:2] ),
      .ENB ( BRAM_EN_B ),
      .SSRB ( BRAM_Rst_B ),
      .WEB ( BRAM_WEN_B[7] )
    );
  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_30 is WRITE_FIRST;
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_30 is WRITE_FIRST;


  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_31 is "WRITE_FIRST";
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_31 is "WRITE_FIRST";
  RAMB16_S2_S2
    ramb16_s2_s2_31 (
      .ADDRA ( BRAM_Addr_A[16:28] ),
      .CLKA ( BRAM_Clk_A ),
      .DIA ( dina[1:0] ),
      .DOA ( douta[1:0] ),
      .ENA ( BRAM_EN_A ),
      .SSRA ( BRAM_Rst_A ),
      .WEA ( BRAM_WEN_A[7] ),
      .ADDRB ( BRAM_Addr_B[16:28] ),
      .CLKB ( BRAM_Clk_B ),
      .DIB ( dinb[1:0] ),
      .DOB ( doutb[1:0] ),
      .ENB ( BRAM_EN_B ),
      .SSRB ( BRAM_Rst_B ),
      .WEB ( BRAM_WEN_B[7] )
    );
  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_31 is WRITE_FIRST;
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_31 is WRITE_FIRST;


endmodule