plb_bram_if_cntlr_1_bram_elaborate.v

基于Xilinx-XUPV2P开发平台的嵌入式系统实验例程：实验4编写基本的应用程序

//-----------------------------------------------------------------------------
// plb_bram_if_cntlr_1_bram_elaborate.v
//-----------------------------------------------------------------------------

module plb_bram_if_cntlr_1_bram_elaborate
  (
    BRAM_Rst_A,
    BRAM_Clk_A,
    BRAM_EN_A,
    BRAM_WEN_A,
    BRAM_Addr_A,
    BRAM_Din_A,
    BRAM_Dout_A,
    BRAM_Rst_B,
    BRAM_Clk_B,
    BRAM_EN_B,
    BRAM_WEN_B,
    BRAM_Addr_B,
    BRAM_Din_B,
    BRAM_Dout_B
  );
  parameter
    C_MEMSIZE = 'h10000,
    C_PORT_DWIDTH = 64,
    C_PORT_AWIDTH = 32,
    C_NUM_WE = 8,
    C_FAMILY = "virtex2p";
  input BRAM_Rst_A;
  input BRAM_Clk_A;
  input BRAM_EN_A;
  input [0:C_NUM_WE-1] BRAM_WEN_A;
  input [0:C_PORT_AWIDTH-1] BRAM_Addr_A;
  output [0:C_PORT_DWIDTH-1] BRAM_Din_A;
  input [0:C_PORT_DWIDTH-1] BRAM_Dout_A;
  input BRAM_Rst_B;
  input BRAM_Clk_B;
  input BRAM_EN_B;
  input [0:C_NUM_WE-1] BRAM_WEN_B;
  input [0:C_PORT_AWIDTH-1] BRAM_Addr_B;
  output [0:C_PORT_DWIDTH-1] BRAM_Din_B;
  input [0:C_PORT_DWIDTH-1] BRAM_Dout_B;

  // Internal signals

  wire [63:0] dina;
  wire [63:0] dinb;
  wire [63:0] douta;
  wire [63:0] doutb;

  // Internal assignments

  assign dina[63:0] = BRAM_Dout_A[0:63];
  assign BRAM_Din_A[0:63] = douta[63:0];
  assign dinb[63:0] = BRAM_Dout_B[0:63];
  assign BRAM_Din_B[0:63] = doutb[63:0];

  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_0 is "WRITE_FIRST";
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_0 is "WRITE_FIRST";
  RAMB16_S2_S2
    ramb16_s2_s2_0 (
      .ADDRA ( BRAM_Addr_A[16:28] ),
      .CLKA ( BRAM_Clk_A ),
      .DIA ( dina[63:62] ),
      .DOA ( douta[63:62] ),
      .ENA ( BRAM_EN_A ),
      .SSRA ( BRAM_Rst_A ),
      .WEA ( BRAM_WEN_A[0] ),
      .ADDRB ( BRAM_Addr_B[16:28] ),
      .CLKB ( BRAM_Clk_B ),
      .DIB ( dinb[63:62] ),
      .DOB ( doutb[63:62] ),
      .ENB ( BRAM_EN_B ),
      .SSRB ( BRAM_Rst_B ),
      .WEB ( BRAM_WEN_B[0] )
    );
  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_0 is WRITE_FIRST;
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_0 is WRITE_FIRST;


  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_1 is "WRITE_FIRST";
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_1 is "WRITE_FIRST";
  RAMB16_S2_S2
    ramb16_s2_s2_1 (
      .ADDRA ( BRAM_Addr_A[16:28] ),
      .CLKA ( BRAM_Clk_A ),
      .DIA ( dina[61:60] ),
      .DOA ( douta[61:60] ),
      .ENA ( BRAM_EN_A ),
      .SSRA ( BRAM_Rst_A ),
      .WEA ( BRAM_WEN_A[0] ),
      .ADDRB ( BRAM_Addr_B[16:28] ),
      .CLKB ( BRAM_Clk_B ),
      .DIB ( dinb[61:60] ),
      .DOB ( doutb[61:60] ),
      .ENB ( BRAM_EN_B ),
      .SSRB ( BRAM_Rst_B ),
      .WEB ( BRAM_WEN_B[0] )
    );
  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_1 is WRITE_FIRST;
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_1 is WRITE_FIRST;


  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_2 is "WRITE_FIRST";
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_2 is "WRITE_FIRST";
  RAMB16_S2_S2
    ramb16_s2_s2_2 (
      .ADDRA ( BRAM_Addr_A[16:28] ),
      .CLKA ( BRAM_Clk_A ),
      .DIA ( dina[59:58] ),
      .DOA ( douta[59:58] ),
      .ENA ( BRAM_EN_A ),
      .SSRA ( BRAM_Rst_A ),
      .WEA ( BRAM_WEN_A[0] ),
      .ADDRB ( BRAM_Addr_B[16:28] ),
      .CLKB ( BRAM_Clk_B ),
      .DIB ( dinb[59:58] ),
      .DOB ( doutb[59:58] ),
      .ENB ( BRAM_EN_B ),
      .SSRB ( BRAM_Rst_B ),
      .WEB ( BRAM_WEN_B[0] )
    );
  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_2 is WRITE_FIRST;
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_2 is WRITE_FIRST;


  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_3 is "WRITE_FIRST";
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_3 is "WRITE_FIRST";
  RAMB16_S2_S2
    ramb16_s2_s2_3 (
      .ADDRA ( BRAM_Addr_A[16:28] ),
      .CLKA ( BRAM_Clk_A ),
      .DIA ( dina[57:56] ),
      .DOA ( douta[57:56] ),
      .ENA ( BRAM_EN_A ),
      .SSRA ( BRAM_Rst_A ),
      .WEA ( BRAM_WEN_A[0] ),
      .ADDRB ( BRAM_Addr_B[16:28] ),
      .CLKB ( BRAM_Clk_B ),
      .DIB ( dinb[57:56] ),
      .DOB ( doutb[57:56] ),
      .ENB ( BRAM_EN_B ),
      .SSRB ( BRAM_Rst_B ),
      .WEB ( BRAM_WEN_B[0] )
    );
  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_3 is WRITE_FIRST;
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_3 is WRITE_FIRST;


  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_4 is "WRITE_FIRST";
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_4 is "WRITE_FIRST";
  RAMB16_S2_S2
    ramb16_s2_s2_4 (
      .ADDRA ( BRAM_Addr_A[16:28] ),
      .CLKA ( BRAM_Clk_A ),
      .DIA ( dina[55:54] ),
      .DOA ( douta[55:54] ),
      .ENA ( BRAM_EN_A ),
      .SSRA ( BRAM_Rst_A ),
      .WEA ( BRAM_WEN_A[1] ),
      .ADDRB ( BRAM_Addr_B[16:28] ),
      .CLKB ( BRAM_Clk_B ),
      .DIB ( dinb[55:54] ),
      .DOB ( doutb[55:54] ),
      .ENB ( BRAM_EN_B ),
      .SSRB ( BRAM_Rst_B ),
      .WEB ( BRAM_WEN_B[1] )
    );
  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_4 is WRITE_FIRST;
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_4 is WRITE_FIRST;


  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_5 is "WRITE_FIRST";
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_5 is "WRITE_FIRST";
  RAMB16_S2_S2
    ramb16_s2_s2_5 (
      .ADDRA ( BRAM_Addr_A[16:28] ),
      .CLKA ( BRAM_Clk_A ),
      .DIA ( dina[53:52] ),
      .DOA ( douta[53:52] ),
      .ENA ( BRAM_EN_A ),
      .SSRA ( BRAM_Rst_A ),
      .WEA ( BRAM_WEN_A[1] ),
      .ADDRB ( BRAM_Addr_B[16:28] ),
      .CLKB ( BRAM_Clk_B ),
      .DIB ( dinb[53:52] ),
      .DOB ( doutb[53:52] ),
      .ENB ( BRAM_EN_B ),
      .SSRB ( BRAM_Rst_B ),
      .WEB ( BRAM_WEN_B[1] )
    );
  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_5 is WRITE_FIRST;
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_5 is WRITE_FIRST;


  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_6 is "WRITE_FIRST";
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_6 is "WRITE_FIRST";
  RAMB16_S2_S2
    ramb16_s2_s2_6 (
      .ADDRA ( BRAM_Addr_A[16:28] ),
      .CLKA ( BRAM_Clk_A ),
      .DIA ( dina[51:50] ),
      .DOA ( douta[51:50] ),
      .ENA ( BRAM_EN_A ),
      .SSRA ( BRAM_Rst_A ),
      .WEA ( BRAM_WEN_A[1] ),
      .ADDRB ( BRAM_Addr_B[16:28] ),
      .CLKB ( BRAM_Clk_B ),
      .DIB ( dinb[51:50] ),
      .DOB ( doutb[51:50] ),
      .ENB ( BRAM_EN_B ),
      .SSRB ( BRAM_Rst_B ),
      .WEB ( BRAM_WEN_B[1] )
    );
  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_6 is WRITE_FIRST;
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_6 is WRITE_FIRST;


  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_7 is "WRITE_FIRST";
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_7 is "WRITE_FIRST";
  RAMB16_S2_S2
    ramb16_s2_s2_7 (
      .ADDRA ( BRAM_Addr_A[16:28] ),
      .CLKA ( BRAM_Clk_A ),
      .DIA ( dina[49:48] ),
      .DOA ( douta[49:48] ),
      .ENA ( BRAM_EN_A ),
      .SSRA ( BRAM_Rst_A ),
      .WEA ( BRAM_WEN_A[1] ),
      .ADDRB ( BRAM_Addr_B[16:28] ),
      .CLKB ( BRAM_Clk_B ),
      .DIB ( dinb[49:48] ),
      .DOB ( doutb[49:48] ),
      .ENB ( BRAM_EN_B ),
      .SSRB ( BRAM_Rst_B ),
      .WEB ( BRAM_WEN_B[1] )
    );
  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_7 is WRITE_FIRST;
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_7 is WRITE_FIRST;


  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_8 is "WRITE_FIRST";
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_8 is "WRITE_FIRST";
  RAMB16_S2_S2
    ramb16_s2_s2_8 (
      .ADDRA ( BRAM_Addr_A[16:28] ),
      .CLKA ( BRAM_Clk_A ),
      .DIA ( dina[47:46] ),
      .DOA ( douta[47:46] ),
      .ENA ( BRAM_EN_A ),
      .SSRA ( BRAM_Rst_A ),
      .WEA ( BRAM_WEN_A[2] ),
      .ADDRB ( BRAM_Addr_B[16:28] ),
      .CLKB ( BRAM_Clk_B ),
      .DIB ( dinb[47:46] ),
      .DOB ( doutb[47:46] ),
      .ENB ( BRAM_EN_B ),
      .SSRB ( BRAM_Rst_B ),
      .WEB ( BRAM_WEN_B[2] )
    );
  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_8 is WRITE_FIRST;
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_8 is WRITE_FIRST;


  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_9 is "WRITE_FIRST";
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_9 is "WRITE_FIRST";
  RAMB16_S2_S2
    ramb16_s2_s2_9 (
      .ADDRA ( BRAM_Addr_A[16:28] ),
      .CLKA ( BRAM_Clk_A ),
      .DIA ( dina[45:44] ),
      .DOA ( douta[45:44] ),
      .ENA ( BRAM_EN_A ),
      .SSRA ( BRAM_Rst_A ),
      .WEA ( BRAM_WEN_A[2] ),
      .ADDRB ( BRAM_Addr_B[16:28] ),
      .CLKB ( BRAM_Clk_B ),
      .DIB ( dinb[45:44] ),
      .DOB ( doutb[45:44] ),
      .ENB ( BRAM_EN_B ),
      .SSRB ( BRAM_Rst_B ),
      .WEB ( BRAM_WEN_B[2] )
    );
  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_9 is WRITE_FIRST;
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_9 is WRITE_FIRST;


  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_10 is "WRITE_FIRST";
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_10 is "WRITE_FIRST";
  RAMB16_S2_S2
    ramb16_s2_s2_10 (
      .ADDRA ( BRAM_Addr_A[16:28] ),
      .CLKA ( BRAM_Clk_A ),
      .DIA ( dina[43:42] ),
      .DOA ( douta[43:42] ),
      .ENA ( BRAM_EN_A ),
      .SSRA ( BRAM_Rst_A ),
      .WEA ( BRAM_WEN_A[2] ),
      .ADDRB ( BRAM_Addr_B[16:28] ),
      .CLKB ( BRAM_Clk_B ),
      .DIB ( dinb[43:42] ),
      .DOB ( doutb[43:42] ),
      .ENB ( BRAM_EN_B ),
      .SSRB ( BRAM_Rst_B ),
      .WEB ( BRAM_WEN_B[2] )
    );
  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_10 is WRITE_FIRST;
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_10 is WRITE_FIRST;


  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_11 is "WRITE_FIRST";
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_11 is "WRITE_FIRST";
  RAMB16_S2_S2
    ramb16_s2_s2_11 (
      .ADDRA ( BRAM_Addr_A[16:28] ),
      .CLKA ( BRAM_Clk_A ),
      .DIA ( dina[41:40] ),
      .DOA ( douta[41:40] ),
      .ENA ( BRAM_EN_A ),
      .SSRA ( BRAM_Rst_A ),
      .WEA ( BRAM_WEN_A[2] ),
      .ADDRB ( BRAM_Addr_B[16:28] ),
      .CLKB ( BRAM_Clk_B ),
      .DIB ( dinb[41:40] ),
      .DOB ( doutb[41:40] ),
      .ENB ( BRAM_EN_B ),
      .SSRB ( BRAM_Rst_B ),
      .WEB ( BRAM_WEN_B[2] )
    );
  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_11 is WRITE_FIRST;
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_11 is WRITE_FIRST;


  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_12 is "WRITE_FIRST";
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_12 is "WRITE_FIRST";
  RAMB16_S2_S2
    ramb16_s2_s2_12 (
      .ADDRA ( BRAM_Addr_A[16:28] ),
      .CLKA ( BRAM_Clk_A ),
      .DIA ( dina[39:38] ),
      .DOA ( douta[39:38] ),
      .ENA ( BRAM_EN_A ),
      .SSRA ( BRAM_Rst_A ),
      .WEA ( BRAM_WEN_A[3] ),
      .ADDRB ( BRAM_Addr_B[16:28] ),
      .CLKB ( BRAM_Clk_B ),
      .DIB ( dinb[39:38] ),
      .DOB ( doutb[39:38] ),
      .ENB ( BRAM_EN_B ),
      .SSRB ( BRAM_Rst_B ),
      .WEB ( BRAM_WEN_B[3] )
    );
  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_12 is WRITE_FIRST;
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_12 is WRITE_FIRST;


  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_13 is "WRITE_FIRST";
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_13 is "WRITE_FIRST";
  RAMB16_S2_S2
    ramb16_s2_s2_13 (
      .ADDRA ( BRAM_Addr_A[16:28] ),
      .CLKA ( BRAM_Clk_A ),
      .DIA ( dina[37:36] ),
      .DOA ( douta[37:36] ),
      .ENA ( BRAM_EN_A ),
      .SSRA ( BRAM_Rst_A ),
      .WEA ( BRAM_WEN_A[3] ),
      .ADDRB ( BRAM_Addr_B[16:28] ),
      .CLKB ( BRAM_Clk_B ),
      .DIB ( dinb[37:36] ),
      .DOB ( doutb[37:36] ),
      .ENB ( BRAM_EN_B ),
      .SSRB ( BRAM_Rst_B ),
      .WEB ( BRAM_WEN_B[3] )
    );
  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_13 is WRITE_FIRST;
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_13 is WRITE_FIRST;


  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_14 is "WRITE_FIRST";
  // synthesis attribute WRITE_MODE_B of ramb16_s2_s2_14 is "WRITE_FIRST";
  RAMB16_S2_S2
    ramb16_s2_s2_14 (
      .ADDRA ( BRAM_Addr_A[16:28] ),
      .CLKA ( BRAM_Clk_A ),
      .DIA ( dina[35:34] ),
      .DOA ( douta[35:34] ),
      .ENA ( BRAM_EN_A ),
      .SSRA ( BRAM_Rst_A ),
      .WEA ( BRAM_WEN_A[3] ),
      .ADDRB ( BRAM_Addr_B[16:28] ),
      .CLKB ( BRAM_Clk_B ),
      .DIB ( dinb[35:34] ),
      .DOB ( doutb[35:34] ),
      .ENB ( BRAM_EN_B ),
      .SSRB ( BRAM_Rst_B ),
      .WEB ( BRAM_WEN_B[3] )
    );
  // synthesis attribute WRITE_MODE_A of ramb16_s2_s2_14 is WRITE_FIRST;