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📄 lpc2103.h

📁 在IAR EWARM开发环境下的ucos_2操作系统在LPC2200上的应用
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__IO_REG32_BIT(PINSEL0,         0xE002C000,__READ_WRITE,__pinsel0_bits);
__IO_REG32_BIT(PINSEL1,         0xE002C004,__READ_WRITE,__pinsel1_bits);

/***************************************************************************
 **
 ** GPIO
 **
 ***************************************************************************/
__IO_REG32_BIT(IOPIN,           0xE0028000,__READ      ,__gpio_bits);
__IO_REG32_BIT(IOSET,           0xE0028004,__READ_WRITE,__gpio_bits);
__IO_REG32_BIT(IODIR,           0xE0028008,__READ_WRITE,__gpio_bits);
__IO_REG32_BIT(IOCLR,           0xE002800C,__WRITE     ,__gpio_bits);
__IO_REG32_BIT(FIODIR,          0x3FFFC000,__READ_WRITE,__fgpio_bits);
#define FIODIR0           FIODIR_bit.__byte0
#define FIODIR0_bit       FIODIR_bit.__byte0_bit
#define FIODIR1           FIODIR_bit.__byte1
#define FIODIR1_bit       FIODIR_bit.__byte1_bit
#define FIODIR2           FIODIR_bit.__byte2
#define FIODIR2_bit       FIODIR_bit.__byte2_bit
#define FIODIR3           FIODIR_bit.__byte3
#define FIODIR3_bit       FIODIR_bit.__byte3_bit
#define FIODIRL           FIODIR_bit.__shortl
#define FIODIRL_bit       FIODIR_bit.__shortl_bit
#define FIODIRU           FIODIR_bit.__shortu
#define FIODIRU_bit       FIODIR_bit.__shortu_bit
__IO_REG32_BIT(FIOMASK,         0x3FFFC010,__READ_WRITE,__fgpio_bits);
#define FIOMASK0          FIOMASK_bit.__byte0
#define FIOMASK0_bit      FIOMASK_bit.__byte0_bit
#define FIOMASK1          FIOMASK_bit.__byte1
#define FIOMASK1_bit      FIOMASK_bit.__byte1_bit
#define FIOMASK2          FIOMASK_bit.__byte2
#define FIOMASK2_bit      FIOMASK_bit.__byte2_bit
#define FIOMASK3          FIOMASK_bit.__byte3
#define FIOMASK3_bit      FIOMASK_bit.__byte3_bit
#define FIOMASKL          FIOMASK_bit.__shortl
#define FIOMASKL_bit      FIOMASK_bit.__shortl_bit
#define FIOMASKU          FIOMASK_bit.__shortu
#define FIOMASKU_bit      FIOMASK_bit.__shortu_bit
__IO_REG32_BIT(FIOPIN,          0x3FFFC014,__READ_WRITE,__fgpio_bits);
#define FIOPIN0           FIOPIN_bit.__byte0
#define FIOPIN0_bit       FIOPIN_bit.__byte0_bit
#define FIOPIN1           FIOPIN_bit.__byte1
#define FIOPIN1_bit       FIOPIN_bit.__byte1_bit
#define FIOPIN2           FIOPIN_bit.__byte2
#define FIOPIN2_bit       FIOPIN_bit.__byte2_bit
#define FIOPIN3           FIOPIN_bit.__byte3
#define FIOPIN3_bit       FIOPIN_bit.__byte3_bit
#define FIOPINL           FIOPIN_bit.__shortl
#define FIOPINL_bit       FIOPIN_bit.__shortl_bit
#define FIOPINU           FIOPIN_bit.__shortu
#define FIOPINU_bit       FIOPIN_bit.__shortu_bit
__IO_REG32_BIT(FIOSET,          0x3FFFC018,__READ_WRITE,__fgpio_bits);
#define FIOSET0           FIOSET_bit.__byte0
#define FIOSET0_bit       FIOSET_bit.__byte0_bit
#define FIOSET1           FIOSET_bit.__byte1
#define FIOSET1_bit       FIOSET_bit.__byte1_bit
#define FIOSET2           FIOSET_bit.__byte2
#define FIOSET2_bit       FIOSET_bit.__byte2_bit
#define FIOSET3           FIOSET_bit.__byte3
#define FIOSET3_bit       FIOSET_bit.__byte3_bit
#define FIOSETL           FIOSET_bit.__shortl
#define FIOSETL_bit       FIOSET_bit.__shortl_bit
#define FIOSETU           FIOSET_bit.__shortu
#define FIOSETU_bit       FIOSET_bit.__shortu_bit
__IO_REG32_BIT(FIOCLR,          0x3FFFC01C,__WRITE     ,__fgpio_bits);
#define FIOCLR0           FIOCLR_bit.__byte0
#define FIOCLR0_bit       FIOCLR_bit.__byte0_bit
#define FIOCLR1           FIOCLR_bit.__byte1
#define FIOCLR1_bit       FIOCLR_bit.__byte1_bit
#define FIOCLR2           FIOCLR_bit.__byte2
#define FIOCLR2_bit       FIOCLR_bit.__byte2_bit
#define FIOCLR3           FIOCLR_bit.__byte3
#define FIOCLR3_bit       FIOCLR_bit.__byte3_bit
#define FIOCLRL           FIOCLR_bit.__shortl
#define FIOCLRL_bit       FIOCLR_bit.__shortl_bit
#define FIOCLRU           FIOCLR_bit.__shortu
#define FIOCLRU_bit       FIOCLR_bit.__shortu_bit

/***************************************************************************
 **
 **  UART0
 **
 ***************************************************************************/
/* U0DLL, U0RBR and U0THR share the same address */
__IO_REG8(     U0RBRTHR,        0xE000C000,__READ_WRITE);
#define U0DLL  U0RBRTHR
#define U0RBR  U0RBRTHR
#define U0THR  U0RBRTHR

/* U0DLM and U0IER share the same address */
__IO_REG32_BIT(U0IER,           0xE000C004,__READ_WRITE,__uartier0_bits);
#define U0DLM  U0IER

/* U0FCR and U0IIR share the same address */
__IO_REG32_BIT(U0FCR,           0xE000C008,__READ_WRITE,__uartfcriir_bits);
#define U0IIR_bit  U0FCR_bit
#define U0IIR      U0FCR

__IO_REG8_BIT( U0LCR,           0xE000C00C,__READ_WRITE,__uartlcr_bits);
__IO_REG8_BIT( U0LSR,           0xE000C014,__READ      ,__uartlsr_bits);
__IO_REG8(     U0SCR,           0xE000C01C,__READ_WRITE);
__IO_REG32_BIT(U0ACR,           0xE000C020,__READ_WRITE,__uartacr_bits);
__IO_REG32_BIT(U0FDR,           0xE000C028,__READ_WRITE,__uartfdr_bits);
__IO_REG8_BIT( U0TER,           0xE000C030,__READ_WRITE,__uartter_bits);

/***************************************************************************
 **
 **  UART1
 **
 ***************************************************************************/
/* U1DLL, U1RBR and U1THR share the same address */
__IO_REG8(     U1RBRTHR,        0xE0010000,__READ_WRITE);
#define U1DLL  U1RBRTHR
#define U1RBR  U1RBRTHR
#define U1THR  U1RBRTHR

/* U1DLM and U1IER share the same address */
__IO_REG32_BIT(U1IER,           0xE0010004,__READ_WRITE,__uartier1_bits);
#define U1DLM  U1IER

/* U1FCR and U1IIR share the same address */
__IO_REG32_BIT(U1FCR,           0xE0010008,__READ_WRITE,__uartfcriir_bits);
#define U1IIR_bit  U1FCR_bit
#define U1IIR      U1FCR

__IO_REG8_BIT( U1LCR,           0xE001000C,__READ_WRITE,__uartlcr_bits);
__IO_REG8_BIT( U1LSR,           0xE0010014,__READ      ,__uartlsr_bits);
__IO_REG8(     U1SCR,           0xE001001C,__READ_WRITE);
__IO_REG32_BIT(U1ACR,           0xE0010020,__READ_WRITE,__uartacr_bits);
__IO_REG32_BIT(U1FDR,           0xE0010028,__READ_WRITE,__uartfdr_bits);
__IO_REG8_BIT( U1TER,           0xE0010030,__READ_WRITE,__uartter_bits);

/***************************************************************************
 **
 ** I2C0
 **
 ***************************************************************************/
__IO_REG32_BIT(I2C0CONSET,      0xE001C000,__READ_WRITE,__i2conset_bits);
__IO_REG32_BIT(I2C0STAT,        0xE001C004,__READ      ,__i2stat_bits);
__IO_REG32_BIT(I2C0DAT,         0xE001C008,__READ_WRITE,__i2dat_bits);
__IO_REG32_BIT(I2C0ADR,         0xE001C00C,__READ_WRITE,__i2adr_bits);
__IO_REG32_BIT(I2C0SCLH,        0xE001C010,__READ_WRITE,__i2scl_bits);
__IO_REG32_BIT(I2C0SCLL,        0xE001C014,__READ_WRITE,__i2scl_bits);
__IO_REG32_BIT(I2C0CONCLR,      0xE001C018,__WRITE     ,__i2conclr_bits);

/***************************************************************************
 **
 ** I2C1
 **
 ***************************************************************************/
__IO_REG32_BIT(I2C1CONSET,      0xE005C000,__READ_WRITE,__i2conset_bits);
__IO_REG32_BIT(I2C1STAT,        0xE005C004,__READ      ,__i2stat_bits);
__IO_REG32_BIT(I2C1DAT,         0xE005C008,__READ_WRITE,__i2dat_bits);
__IO_REG32_BIT(I2C1ADR,         0xE005C00C,__READ_WRITE,__i2adr_bits);
__IO_REG32_BIT(I2C1SCLH,        0xE005C010,__READ_WRITE,__i2scl_bits);
__IO_REG32_BIT(I2C1SCLL,        0xE005C014,__READ_WRITE,__i2scl_bits);
__IO_REG32_BIT(I2C1CONCLR,      0xE005C018,__WRITE     ,__i2conclr_bits);

/***************************************************************************
 **
 ** SPI
 **
 ***************************************************************************/
__IO_REG32_BIT(S0SPCR,          0xE0020000,__READ_WRITE,__spcr_bits);
__IO_REG32_BIT(S0SPSR,          0xE0020004,__READ      ,__spsr_bits);
__IO_REG32_BIT(S0SPDR,          0xE0020008,__READ_WRITE,__spdr_bits);
__IO_REG32_BIT(S0SPCCR,         0xE002000C,__READ_WRITE,__spccr_bits);
__IO_REG32_BIT(S0SPINT,         0xE002001C,__READ_WRITE,__spint_bits);

/***************************************************************************
 **
 ** SSP
 **
 ***************************************************************************/
__IO_REG32_BIT(SSPCR0,          0xE0068000,__READ_WRITE,__sspcr0_bits);
__IO_REG32_BIT(SSPCR1,          0xE0068004,__READ_WRITE,__sspcr1_bits);
__IO_REG32_BIT(SSPDR,           0xE0068008,__READ_WRITE,__sspdr_bits);
__IO_REG32_BIT(SSPSR,           0xE006800C,__READ      ,__sspsr_bits);
__IO_REG32_BIT(SSPCPSR,         0xE0068010,__READ_WRITE,__sspcpsr_bits);
__IO_REG32_BIT(SSPIMSC,         0xE0068014,__READ_WRITE,__sspimsc_bits);
__IO_REG32_BIT(SSPRIS,          0xE0068018,__READ_WRITE,__sspris_bits);
__IO_REG32_BIT(SSPMIS,          0xE006801C,__READ      ,__sspmis_bits);
__IO_REG32_BIT(SSPICR,          0xE0068020,__WRITE     ,__sspicr_bits);

/***************************************************************************
 **
 ** A/D Converters
 **
 ***************************************************************************/
__IO_REG32_BIT(AD0CR,           0xE0034000,__READ_WRITE,__adcr_bits);
__IO_REG32_BIT(AD0GDR,          0xE0034004,__READ_WRITE,__adgdr_bits);
__IO_REG32_BIT(ADINTEN,         0xE003400C,__READ_WRITE,__adinten_bits);
__IO_REG32_BIT(ADDR0,           0xE0034010,__READ      ,__addr_bits);
__IO_REG32_BIT(ADDR1,           0xE0034014,__READ      ,__addr_bits);
__IO_REG32_BIT(ADDR2,           0xE0034018,__READ      ,__addr_bits);
__IO_REG32_BIT(ADDR3,           0xE003401C,__READ      ,__addr_bits);
__IO_REG32_BIT(ADDR4,           0xE0034020,__READ      ,__addr_bits);
__IO_REG32_BIT(ADDR5,           0xE0034024,__READ      ,__addr_bits);
__IO_REG32_BIT(ADDR6,           0xE0034028,__READ      ,__addr_bits);
__IO_REG32_BIT(ADDR7,           0xE003402C,__READ      ,__addr_bits);
__IO_REG32_BIT(ADSTAT,          0xE0034030,__READ      ,__adstat_bits);

/***************************************************************************
 **
 ** TIMER0
 **
 ***************************************************************************/
__IO_REG32_BIT(T0IR,            0xE0004000,__READ_WRITE,__ir0_bits);
__IO_REG32_BIT(T0TCR,           0xE0004004,__READ_WRITE,__tcr_bits);
__IO_REG32(    T0TC,            0xE0004008,__READ_WRITE);
__IO_REG32(    T0PR,            0xE000400c,__READ_WRITE);
__IO_REG32(    T0PC,            0xE0004010,__READ_WRITE);
__IO_REG32_BIT(T0MCR,           0xE0004014,__READ_WRITE,__mcr_bits);
__IO_REG32(    T0MR0,           0xE0004018,__READ_WRITE);
__IO_REG32(    T0MR1,           0xE000401C,__READ_WRITE);
__IO_REG32(    T0MR2,           0xE0004020,__READ_WRITE);
__IO_REG32(    T0MR3,           0xE0004024,__READ_WRITE);
__IO_REG32_BIT(T0CCR,           0xE0004028,__READ_WRITE,__ccr0_bits);
__IO_REG32(    T0CR0,           0xE000402C,__READ      );
__IO_REG32(    T0CR1,           0xE0004030,__READ      );
__IO_REG32(    T0CR2,           0xE0004034,__READ      );
__IO_REG32_BIT(T0EMR,           0xE000403c,__READ_WRITE,__emr_bits);
__IO_REG32_BIT(T0CTCR,          0xE0004070,__READ_WRITE,__tctcr_bits);
__IO_REG32_BIT(T0PWMCON,        0xE0004074,__READ_WRITE,__tpwrcon_bits);

/***************************************************************************
 **
 ** TIMER1
 **
 ***************************************************************************/
__IO_REG32_BIT(T1IR,            0xE0008000,__READ_WRITE,__ir1_bits);
__IO_REG32_BIT(T1TCR,           0xE0008004,__READ_WRITE,__tcr_bits);
__IO_REG32(    T1TC,            0xE0008008,__READ_WRITE);
__IO_REG32(    T1PR,            0xE000800c,__READ_WRITE);
__IO_REG32(    T1PC,            0xE0008010,__READ_WRITE);
__IO_REG32_BIT(T1MCR,           0xE0008014,__READ_WRITE,__mcr_bits);
__IO_REG32(    T1MR0,           0xE0008018,__READ_WRITE);
__IO_REG32(    T1MR1,           0xE000801C,__READ_WRITE);
__IO_REG32(    T1MR2,           0xE0008020,__READ_WRITE);
__IO_REG32(    T1MR3,           0xE0008024,__READ_WRITE);
__IO_REG32_BIT(T1CCR,           0xE0008028,__READ_WRITE,__ccr1_bits);
__IO_REG32(    T1CR0,           0xE000802C,__READ      );
__IO_REG32(    T1CR1,           0xE0008030,__READ      );
__IO_REG32(    T1CR2,           0xE0008034,__READ      );
__IO_REG32(    T1CR3,           0xE0008038,__READ      );
__IO_REG32_BIT(T1EMR,           0xE000803c,__READ_WRITE,__emr_bits);
__IO_REG32_BIT(T1CTCR,          0xE0008070,__READ_WRITE,__tctcr_bits);
__IO_REG32_BIT(T1PWMCON,        0xE0008074,__READ_WRITE,__tpwrcon_bits);

/***************************************************************************
 **
 ** TIMER2
 **
 ***************************************************************************/
__IO_REG32_BIT(T2IR,            0xE0070000,__READ_WRITE,__ir0_bits);
__IO_REG32_BIT(T2TCR,           0xE0070004,__READ_WRITE,__tcr_bits);
__IO_REG32(    T2TC,            0xE0070008,__READ_WRITE);
__IO_REG32(    T2PR,            0xE007000c,__READ_WRITE);
__IO_REG32(    T2PC,            0xE0070010,__READ_WRITE);
__IO_REG32_BIT(T2MCR,           0xE0070014,__READ_WRITE,__mcr_bits);
__IO_REG32(    T2MR0,           0xE0070018,__READ_WRITE);
__IO_REG32(    T2MR1,           0xE007001C,__READ_WRITE);
__IO_REG32(    T2MR2,           0xE0070020,__READ_WRITE);
__IO_REG32(    T2MR3,           0xE0070024,__READ_WRITE);
__IO_REG32_BIT(T2CCR,           0xE0070028,__READ_WRITE,__ccr0_bits);
__IO_REG32(    T2CR0,           0xE007002C,__READ      );
__IO_REG32(    T2CR1,           0xE0070030,__READ      );
__IO_REG32(    T2CR2,           0xE0070034,__READ      );
__IO_REG32_BIT(T2EMR,           0xE007003c,__READ_WRITE,__emr_bits);
__IO_REG32_BIT(T2CTCR,          0xE0070070,__READ_WRITE,__tctcr_bits);
__IO_REG32_BIT(T2PWMCON,        0xE0070074,__READ_WRITE,__tpwrcon_bits);

/***************************************************************************
 **
 ** TIMER3
 **
 ***************************************************************************/
__IO_REG32_BIT(T3IR,            0xE0074000,__READ_WRITE,__ir3_bits);
__IO_REG32_BIT(T3TCR,           0xE0074004,__READ_WRITE,__tcr_bits);
__IO_REG32(    T3TC,            0xE0074008,__READ_WRITE);
__IO_REG32(    T3PR,            0xE007400c,__READ_WRITE);
__IO_REG32(    T3PC,            0xE0074010,__READ_WRITE);
__IO_REG32_BIT(T3MCR,           0xE0074014,__READ_WRITE,__mcr_bits);
__IO_REG32(    T3MR0,           0xE0074018,__READ_WRITE);
__IO_REG32(    T3MR1,           0xE007401C,__READ_WRITE);
__IO_REG32(    T3MR2,           0xE0074020,__READ_WRITE);
__IO_REG32(    T3MR3,           0xE0074024,__READ_WRITE);
__IO_REG32_BIT(T3EMR,           0xE007403c,__READ_WRITE,__emr_bits);
__IO_REG32_BIT(T3CTCR,          0xE0074070,__READ_WRITE,__tctcr_bits);
__IO_REG32_BIT(T3PWMCON,        0xE0074074,__READ_WRITE,__tpwrcon_bits);

/***************************************************************************
 **
 ** RTC
 **
 ***************************************************************************/
__IO_REG32_BIT(ILR,             0xE0024000,__READ_WRITE,__ilr_bits);
__IO_REG32_BIT(CTC,             0xE0024004,__READ      ,__ctc_bits);
__IO_REG32_BIT(CCR,             0xE0024008,__READ_WRITE,__rtcccr_bits);
__IO_REG32_BIT(CIIR,            0xE002400C,__READ_WRITE,__ciir_bits);
__IO_REG32_BIT(AMR,             0xE0024010,__READ_WRITE,__amr_bits);
__IO_REG32_BIT(CTIME0,          0xE0024014,__READ      ,__ctime0_bits);
__IO_REG32_BIT(CTIME1,          0xE0024018,__READ      ,__ctime1_bits);
__IO_REG32_BIT(CTIME2,          0xE002401C,__READ      ,__ctime2_bits);
__IO_REG32_BIT(SEC,             0xE0024020,__READ_WRITE,__sec_bits);
__IO_REG32_BIT(MIN,             0xE0024024,__READ_WRITE,__min_bits);
__IO_REG32_BIT(HOUR,            0xE0024028,__READ_WRITE,__hour_bits);
__IO_REG32_BIT(DOM,             0xE002402C,__READ_WRITE,__dom_bits);
__IO_REG32_BIT(DOW,             0xE0024030,__READ_WRITE,__dow_bits);
__IO_REG32_BIT(DOY,             0xE0024034,__READ_WRITE,__doy_bits);
__IO_REG32_BIT(MONTH,           0xE0024038,__READ_WRITE,__month_bits);
__IO_REG32_BIT(YEAR,            0xE002403C,__READ_WRITE,__year_bits);
__IO_REG32_BIT(ALSEC,           0xE0024060,__READ_WRITE,__sec_bits);
__IO_REG32_BIT(ALMIN,           0xE0024064,__READ_WRITE,__min_bits);
__IO_REG32_BIT(ALHOUR,          0xE0024068,__READ_WRITE,__hour_bits);
__IO_REG32_BIT(ALDOM,           0xE002406C,__READ_WRITE,__dom_bits);
__IO_REG32_BIT(ALDOW,           0xE0024070,__READ_WRITE,__dow_bits);
__IO_REG32_BIT(ALDOY,           0xE0024074,__READ_WRITE,__doy_bits);
__IO_REG32_BIT(ALMON,           0xE0024078,__READ_WRITE,__month_bits);
__IO_REG32_BIT(ALYEAR,          0xE002407C,__READ_WRITE,__year_bits);
__IO_REG32_BIT(PREINT,          0xE0024080,__READ_WRITE,__preint_bits);
__IO_REG32_BIT(PREFRAC,         0xE0024084,__READ_WRITE,__prefrac_bits);

/***************************************************************************
 **
 ** Watchdog
 **
 ***************************************************************************/
__IO_REG32_BIT(WDMOD,           0xE0000000,__READ_WRITE,__wdmod_bits);
__IO_REG32(    WDTC,            0xE0000004,__READ_WRITE);
__IO_REG32_BIT(WDFEED,          0xE0000008,__WRITE     ,__wdfeed_bits);
__IO_REG32(    WDTV,            0xE000000C,__READ      );

/***************************************************************************
 **  Assembler specific declarations
 ***************************************************************************/
#ifdef __IAR_SYSTEMS_ASM__

#endif    /* __IAR_SYSTEMS_ASM__ */

/***************************************************************************
 **
 **  Interrupt vector table
 **
 ***************************************************************************/
#define RESETV          0x00  /* Reset                              */
#define UNDEFV          0x04  /* Undefined instruction              */
#define SWIV            0x08  /* Software interrupt                 */
#define PABORTV         0x0c  /* Prefetch abort                     */
#define DABORTV         0x10  /* Data abort                         */
#define IRQV            0x18  /* Normal interrupt                   */
#define FIQV            0x1c  /* Fast interrupt                     */

/***************************************************************************
 **
 **  VIC Interrupt channels
 **
 ***************************************************************************/
#define VIC_WDT          0    /* Watchdog                           */
#define VIC_DEBUGRX      2    /* Embedded ICE, DbgCommRx            */
#define VIC_DEBUGTX      3    /* Embedded ICE, DbgCommTx            */
#define VIC_TIMER0       4    /* Timer 0 (Match 0-2 Capture 0-2)    */
#define VIC_TIMER1       5    /* Timer 1 (Match 0-3 Capture 0-3)    */
#define VIC_UART0        6    /* UART 0  (RLS, THRE, RDA, CTI)      */
#define VIC_UART1        7    /* UART 1  (RLS, THRE, RDA, CTI, MSI) */
#define VIC_I2C0         9    /* I2C     (SI)                       */
#define VIC_SPI         10    /* SPI     (SPIF, MODF)               */
#define VIC_SSP         11    /* SPI1 (SSP)                         */
#define VIC_PLL         12    /* PLL lock (PLOCK)                   */
#define VIC_RTC         13    /* RTC     (RTCCIF, RTCALF)           */
#define VIC_EINT0       14    /* External interrupt 0 (EINT0)       */
#define VIC_EINT1       15    /* External interrupt 1 (EINT1)       */
#define VIC_EINT2       16    /* External interrupt 2 (EINT2)       */
#define VIC_ADC         18    /* A/D Converter 0 end of conversion  */
#define VIC_I2C1        19    /* I2C     (SI)                       */
#define VIC_TIMER2      26    /* Timer 2 (Match 0-2 Capture 0-2)    */
#define VIC_TIMER3      27    /* Timer 3 (Match 0-3)                */

#endif    /* __IOLPC2101_H */

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