📄 lpc2103.h
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__REG32 OVERRUN3 : 1;
__REG32 OVERRUN4 : 1;
__REG32 OVERRUN5 : 1;
__REG32 OVERRUN6 : 1;
__REG32 OVERRUN7 : 1;
__REG32 ADINT : 1;
__REG32 :15;
} __adstat_bits;
/* A/D Intrrupt Enable Register */
typedef struct{
__REG32 ADINTEN0 : 1;
__REG32 ADINTEN1 : 1;
__REG32 ADINTEN2 : 1;
__REG32 ADINTEN3 : 1;
__REG32 ADINTEN4 : 1;
__REG32 ADINTEN5 : 1;
__REG32 ADINTEN6 : 1;
__REG32 ADINTEN7 : 1;
__REG32 ADGINTEN : 1;
__REG32 :23;
} __adinten_bits;
/* A/D Data Register */
typedef struct{
__REG32 : 6;
__REG32 RESULT :10;
__REG32 :14;
__REG32 OVERUN : 1;
__REG32 DONE : 1;
} __addr_bits;
/* TIMER0 Interrupt Register */
typedef struct{
__REG32 MR0INT : 1;
__REG32 MR1INT : 1;
__REG32 MR2INT : 1;
__REG32 MR3INT : 1;
__REG32 CR0INT : 1;
__REG32 CR1INT : 1;
__REG32 CR2INT : 1;
__REG32 :25;
} __ir0_bits;
/* TIMER1 Interrupt Register */
typedef struct{
__REG32 MR0INT : 1;
__REG32 MR1INT : 1;
__REG32 MR2INT : 1;
__REG32 MR3INT : 1;
__REG32 CR0INT : 1;
__REG32 CR1INT : 1;
__REG32 CR2INT : 1;
__REG32 CR3INT : 1;
__REG32 :24;
} __ir1_bits;
/* TIMER3 Interrupt Register */
typedef struct{
__REG32 MR0INT : 1;
__REG32 MR1INT : 1;
__REG32 MR2INT : 1;
__REG32 MR3INT : 1;
__REG32 :28;
} __ir3_bits;
/* TIMER Control Register */
typedef struct{
__REG32 CE : 1;
__REG32 CR : 1;
__REG32 :30;
} __tcr_bits;
/* TIMER Count Control Register */
typedef struct{
__REG32 TM : 2;
__REG32 CIS : 2;
__REG32 :28;
} __tctcr_bits;
/* TIMER Match Control Register */
typedef struct{
__REG32 MR0INT : 1;
__REG32 MR0RES : 1;
__REG32 MR0STOP : 1;
__REG32 MR1INT : 1;
__REG32 MR1RES : 1;
__REG32 MR1STOP : 1;
__REG32 MR2INT : 1;
__REG32 MR2RES : 1;
__REG32 MR2STOP : 1;
__REG32 MR3INT : 1;
__REG32 MR3RES : 1;
__REG32 MR3STOP : 1;
__REG32 :20;
} __mcr_bits;
/* TIMER0 Capture Control Register */
typedef struct{
__REG32 CAP0RE : 1;
__REG32 CAP0FE : 1;
__REG32 CAP0INT : 1;
__REG32 CAP1RE : 1;
__REG32 CAP1FE : 1;
__REG32 CAP1INT : 1;
__REG32 CAP2RE : 1;
__REG32 CAP2FE : 1;
__REG32 CAP2INT : 1;
__REG32 :23;
} __ccr0_bits;
/* TIMER1 Capture Control Register */
typedef struct{
__REG32 CAP0RE : 1;
__REG32 CAP0FE : 1;
__REG32 CAP0INT : 1;
__REG32 CAP1RE : 1;
__REG32 CAP1FE : 1;
__REG32 CAP1INT : 1;
__REG32 CAP2RE : 1;
__REG32 CAP2FE : 1;
__REG32 CAP2INT : 1;
__REG32 CAP3RE : 1;
__REG32 CAP3FE : 1;
__REG32 CAP3INT : 1;
__REG32 :20;
} __ccr1_bits;
/* TIMER External Match Register */
typedef struct{
__REG32 EM0 : 1;
__REG32 EM1 : 1;
__REG32 EM2 : 1;
__REG32 EM3 : 1;
__REG32 EMC0 : 2;
__REG32 EMC1 : 2;
__REG32 EMC2 : 2;
__REG32 EMC3 : 2;
__REG32 :20;
} __emr_bits;
/* TIMER PWM Control Register */
typedef struct{
__REG32 PWM0ENA : 1;
__REG32 PWM1ENA : 1;
__REG32 PWM2ENA : 1;
__REG32 PWM3ENA : 1;
__REG32 :28;
} __tpwrcon_bits;
/* RTC Interrupt Location Register */
typedef struct{
__REG32 RTCCIF : 1;
__REG32 RTCALF : 1;
__REG32 :30;
} __ilr_bits;
/* RTC Clock Tick Counter Register */
typedef struct{
__REG32 COUNTER :16;
__REG32 :16;
} __ctc_bits;
/* RTC Clock Control Register */
typedef struct{
__REG32 CLKEN : 1;
__REG32 CTCRST : 1;
__REG32 CTTEST : 2;
__REG32 CLKSRC : 1;
__REG32 :27;
} __rtcccr_bits;
/* RTC Counter Increment Interrupt Register */
typedef struct{
__REG32 IMSEC : 1;
__REG32 IMMIN : 1;
__REG32 IMHOUR : 1;
__REG32 IMDOM : 1;
__REG32 IMDOW : 1;
__REG32 IMDOY : 1;
__REG32 IMMON : 1;
__REG32 IMYEAR : 1;
__REG32 :24;
} __ciir_bits;
/* RTC Alarm Mask Register */
typedef struct{
__REG32 AMRSEC : 1;
__REG32 AMRMIN : 1;
__REG32 AMRHOUR : 1;
__REG32 AMRDOM : 1;
__REG32 AMRDOW : 1;
__REG32 AMRDOY : 1;
__REG32 AMRMON : 1;
__REG32 AMRYEAR : 1;
__REG32 :24;
} __amr_bits;
/* RTC Consolidated Time Register 0 */
typedef struct{
__REG32 SEC : 6;
__REG32 : 2;
__REG32 MIN : 6;
__REG32 : 2;
__REG32 HOUR : 5;
__REG32 : 3;
__REG32 DOW : 3;
__REG32 : 5;
} __ctime0_bits;
/* RTC Consolidated Time Register 1 */
typedef struct{
__REG32 DOM : 5;
__REG32 : 3;
__REG32 MON : 4;
__REG32 : 4;
__REG32 YEAR :12;
__REG32 : 4;
} __ctime1_bits;
/* RTC Consolidated Time Register 2 */
typedef struct{
__REG32 DOY :12;
__REG32 :20;
} __ctime2_bits;
/* RTC Second Register */
typedef struct{
__REG32 SEC : 6;
__REG32 :26;
} __sec_bits;
/* RTC Minute Register */
typedef struct{
__REG32 MIN : 6;
__REG32 :26;
} __min_bits;
/* RTC Hour Register */
typedef struct{
__REG32 HOUR : 5;
__REG32 :27;
} __hour_bits;
/* RTC Day Of Month Register */
typedef struct{
__REG32 DOM : 5;
__REG32 :27;
} __dom_bits;
/* RTC Day Of Week Register */
typedef struct{
__REG32 DOW : 3;
__REG32 :29;
} __dow_bits;
/* RTC Day Of Year Register */
typedef struct{
__REG32 DOY : 9;
__REG32 :23;
} __doy_bits;
/* RTC Month Register */
typedef struct{
__REG32 MON : 4;
__REG32 :28;
} __month_bits;
/* RTC Year Register */
typedef struct{
__REG32 YEAR :12;
__REG32 :20;
} __year_bits;
/* RTC Prescaler Value, Integer Portion Register */
typedef struct{
__REG32 VALUE :13;
__REG32 :19;
} __preint_bits;
/* RTC Prescaler Value, Fractional Portion Register */
typedef struct{
__REG32 VALUE :15;
__REG32 :17;
} __prefrac_bits;
/* Watchdog Mode Register */
typedef struct{
__REG32 WDEN : 1;
__REG32 WDRESET : 1;
__REG32 WDTOF : 1;
__REG32 WDINT : 1;
__REG32 :28;
} __wdmod_bits;
/* Watchdog Feed Register */
typedef struct{
__REG32 FEED : 8;
__REG32 :24;
} __wdfeed_bits;
#endif /* __IAR_SYSTEMS_ICC__ */
/* Common declarations ****************************************************/
/***************************************************************************
**
** System control block
**
***************************************************************************/
__IO_REG32_BIT(EXTINT, 0xE01FC140,__READ_WRITE,__extint_bits);
__IO_REG32_BIT(EXTWAKE, 0xE01FC144,__READ_WRITE,__extwake_bits);
__IO_REG32_BIT(EXTMODE, 0xE01FC148,__READ_WRITE,__extmode_bits);
__IO_REG32_BIT(EXTPOLAR, 0xE01FC14C,__READ_WRITE,__extpol_bits);
__IO_REG32_BIT(SCS, 0xE01FC1A0,__READ_WRITE,__scs_bits);
__IO_REG32_BIT(MEMMAP, 0xE01FC040,__READ_WRITE,__memmap_bits);
__IO_REG32_BIT(PLLCON, 0xE01FC080,__READ_WRITE,__pllcon_bits);
__IO_REG32_BIT(PLLCFG, 0xE01FC084,__READ_WRITE,__pllcfg_bits);
__IO_REG32_BIT(PLLSTAT, 0xE01FC088,__READ ,__pllstat_bits);
__IO_REG32_BIT(PLLFEED, 0xE01FC08C,__WRITE ,__pllfeed_bits);
__IO_REG32_BIT(PCON, 0xE01FC0C0,__READ_WRITE,__pcon_bits);
__IO_REG32_BIT(PCONP, 0xE01FC0C4,__READ_WRITE,__pconp_bits);
__IO_REG32_BIT(RSIR, 0xE01FC180,__READ_WRITE,__rsir_bits);
__IO_REG32( CSPR, 0xE01FC184,__READ);
__IO_REG32_BIT(APBDIV, 0xE01FC100,__READ_WRITE,__apbdiv_bits);
__IO_REG32_BIT(MAMCR, 0xE01FC000,__READ_WRITE,__mamcr_bits);
__IO_REG32_BIT(MAMTIM, 0xE01FC004,__READ_WRITE,__mamtim_bits);
/***************************************************************************
**
** VIC
**
***************************************************************************/
__IO_REG32_BIT(VICIRQStatus, 0xFFFFF000,__READ ,__vicint_bits);
__IO_REG32_BIT(VICFIQStatus, 0xFFFFF004,__READ ,__vicint_bits);
__IO_REG32_BIT(VICRawIntr, 0xFFFFF008,__READ ,__vicint_bits);
__IO_REG32_BIT(VICIntSelect, 0xFFFFF00C,__READ_WRITE,__vicint_bits);
__IO_REG32_BIT(VICIntEnable, 0xFFFFF010,__READ_WRITE,__vicint_bits);
__IO_REG32_BIT(VICIntEnClear, 0xFFFFF014,__WRITE ,__vicint_bits);
__IO_REG32_BIT(VICSoftInt, 0xFFFFF018,__READ_WRITE,__vicint_bits);
__IO_REG32_BIT(VICSoftIntClear, 0xFFFFF01C,__WRITE ,__vicint_bits);
__IO_REG32_BIT(VICProtection, 0xFFFFF020,__READ_WRITE,__vicprotection_bits);
__IO_REG32( VICVectAddr, 0xFFFFF030,__READ_WRITE);
__IO_REG32( VICDefVectAddr, 0xFFFFF034,__READ_WRITE);
__IO_REG32( VICVectAddr0, 0xFFFFF100,__READ_WRITE);
__IO_REG32( VICVectAddr1, 0xFFFFF104,__READ_WRITE);
__IO_REG32( VICVectAddr2, 0xFFFFF108,__READ_WRITE);
__IO_REG32( VICVectAddr3, 0xFFFFF10C,__READ_WRITE);
__IO_REG32( VICVectAddr4, 0xFFFFF110,__READ_WRITE);
__IO_REG32( VICVectAddr5, 0xFFFFF114,__READ_WRITE);
__IO_REG32( VICVectAddr6, 0xFFFFF118,__READ_WRITE);
__IO_REG32( VICVectAddr7, 0xFFFFF11C,__READ_WRITE);
__IO_REG32( VICVectAddr8, 0xFFFFF120,__READ_WRITE);
__IO_REG32( VICVectAddr9, 0xFFFFF124,__READ_WRITE);
__IO_REG32( VICVectAddr10, 0xFFFFF128,__READ_WRITE);
__IO_REG32( VICVectAddr11, 0xFFFFF12C,__READ_WRITE);
__IO_REG32( VICVectAddr12, 0xFFFFF130,__READ_WRITE);
__IO_REG32( VICVectAddr13, 0xFFFFF134,__READ_WRITE);
__IO_REG32( VICVectAddr14, 0xFFFFF138,__READ_WRITE);
__IO_REG32( VICVectAddr15, 0xFFFFF13C,__READ_WRITE);
__IO_REG32_BIT(VICVectCntl0, 0xFFFFF200,__READ_WRITE,__vicvectcntl_bits);
__IO_REG32_BIT(VICVectCntl1, 0xFFFFF204,__READ_WRITE,__vicvectcntl_bits);
__IO_REG32_BIT(VICVectCntl2, 0xFFFFF208,__READ_WRITE,__vicvectcntl_bits);
__IO_REG32_BIT(VICVectCntl3, 0xFFFFF20C,__READ_WRITE,__vicvectcntl_bits);
__IO_REG32_BIT(VICVectCntl4, 0xFFFFF210,__READ_WRITE,__vicvectcntl_bits);
__IO_REG32_BIT(VICVectCntl5, 0xFFFFF214,__READ_WRITE,__vicvectcntl_bits);
__IO_REG32_BIT(VICVectCntl6, 0xFFFFF218,__READ_WRITE,__vicvectcntl_bits);
__IO_REG32_BIT(VICVectCntl7, 0xFFFFF21C,__READ_WRITE,__vicvectcntl_bits);
__IO_REG32_BIT(VICVectCntl8, 0xFFFFF220,__READ_WRITE,__vicvectcntl_bits);
__IO_REG32_BIT(VICVectCntl9, 0xFFFFF224,__READ_WRITE,__vicvectcntl_bits);
__IO_REG32_BIT(VICVectCntl10, 0xFFFFF228,__READ_WRITE,__vicvectcntl_bits);
__IO_REG32_BIT(VICVectCntl11, 0xFFFFF22C,__READ_WRITE,__vicvectcntl_bits);
__IO_REG32_BIT(VICVectCntl12, 0xFFFFF230,__READ_WRITE,__vicvectcntl_bits);
__IO_REG32_BIT(VICVectCntl13, 0xFFFFF234,__READ_WRITE,__vicvectcntl_bits);
__IO_REG32_BIT(VICVectCntl14, 0xFFFFF238,__READ_WRITE,__vicvectcntl_bits);
__IO_REG32_BIT(VICVectCntl15, 0xFFFFF23C,__READ_WRITE,__vicvectcntl_bits);
/***************************************************************************
**
** Pin connect block
**
***************************************************************************/
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