📄 zd1.c
字号:
#include "C240.h"
/* define constant value */
#define FALSE 0
#define TRUE 1
#define VELOCITY_CONST 1562500
/* define variable */
unsigned int IA_max,IB_max,IC_max; /* MAX limit for current */
unsigned int IA_min,IB_min,IC_min; /* MIN limit for current */
unsigned int ADC_channel; /* Channel for A/D convert */
int display_times; /* accumulation for display */
int T3overflow_counter; /* T3 overflow times */
int input_state;
int sign_state;
int dot_state;
int CAP1_flag;
int inputdata_num;
unsigned int intput_value;
unsigned int input_dotbit;
unsigned int position_value;
unsigned int position_dotbit;
unsigned int position;
unsigned int velocity_value;
unsigned int velocity_dotbit;
unsigned int int_position;
int display_order; /* 1 while display velocity ,2 while display current ,3 while display input data */
/* define Input/Output variable value */
ioport unsigned int port0,port1,port2,port3,port4,port5;
/* define structure type and variable value */
struct CAP_INT
{
unsigned int PA_value;
unsigned int CAP_value;
long delta_count;
struct CAP_INT * next;
};
struct CAP_INT * CAP_p;
/*********************************************/
void ADC_ISR()
{
unsigned int x1,x2,channel,I_MAX,I_MIN;
x1=ADCTRL1|0x010e;
if (ADC_channel>4)
ADC_channel=2;
channel=ADC_channel;
x2=x1&(ADC_channel<<1); /* ADC_channel=2,3,4 */
ADCTRL1=x2;
ADCTRL2=0x0404; /* Start A/D convert for next channel */
x1=ADCFIFO1;
x2=x1>>6;
switch(channel)
{
case 2:I_MAX=IA_max;
I_MIN=IA_min;
case 3:I_MAX=IB_max;
I_MIN=IB_min;
case 4:I_MAX=IC_max;
I_MIN=IC_min;
default:break;
}
if (x2>=I_MAX)
{
x1=PBDATDIR&(~(1<<(ADC_channel-2)));
PBDATDIR=x1;
}
if (x2<=I_MIN)
{
x1=PBDATDIR|(1<<(ADC_channel-2));
PBDATDIR=x1;
}
ADC_channel++;
}
/*********************************************/
void keyboard_ISR()
{
int i;
static unsigned int clock_PAvalue[6]={0x0706,0x0702,0x0703,0x0701,0x0705,0x0704};
static unsigned int anticlock_PAvalue[6]={0x0706,0x0704,0x0705,0x0701,0x0703,0x0702};
struct CAP_INT * p;
unsigned int scan_in,scan_out;
int row,column=0,key_NO; /* row=0,1,2; column=1,2,3,4 */
row=0;
scan_out=0x0f7f;
port0=scan_out; /* scan keyboard */
scan_in=port0;
while ((scan_in&0x0f)==0xff)
{
port0=scan_out>>1;
scan_in=port0;
row++;
if (row>=4)
{
row=17;
break;
}
}
switch(scan_in & 0x0f)
{
case 0x0e: column=4;
break;
case 0x0d: column=3;
break;
case 0x0b: column=2;
break;
case 0x07: column=1;
break;
default : column=17;
}
for(;;)
{
scan_in=port0;
if ((scan_in & 0x0f)==0x0f)
break;
}
key_NO=4*row+column;
port1=0x00;
port2=0x0f;
switch(key_NO)
{
case 1 : port3=0x0f;
port4=0x01;
break;
case 2 : port3=0x0f;
port4=0x02;
break;
case 3 : port3=0x0f;
port4=0x03;
break;
case 4 : port3=0x0f;
port4=0x04;
break;
case 5 : port3=0x0f;
port4=0x05;
break;
case 6 : port3=0x0f;
port4=0x06;
break;
case 7 : port3=0x0f;
port4=0x07;
break;
case 8 : port3=0x0f;
port4=0x08;
break;
case 9 : port3=0x0f;
port4=0x09;
break;
case 10 : port3=0x01;
port4=0x00;
break;
case 11 : port3=0x01;
port4=0x01;
break;
case 12 : port3=0x01;
port4=0x02;
break;
case 13 : port3=0x01;
port4=0x03;
break;
case 14 : port3=0x01;
port4=0x04;
break;
case 15 : port3=0x01;
port4=0x05;
break;
case 16 : port3=0x01;
port4=0x06;
break;
default : break;
}
}
/*********************************************/
void dsp_setup()
{
unsigned int temp;
/*********************************************/
/* Disable watchdog timer */
/*********************************************/
temp = WDCR;
temp = temp|0x68;
WDCR = temp;
/*********************************************/
/* initialize PLL module (20 MHz XTAL1) */
/*********************************************/
CKCR1 = 0x61; /* crystal=20MHz CPUCLK = 40MHz */
/* and 2x PLL mult ratio */
CKCR0 = 0xc3; /* low–power mode 0, */
/* ACLK enabled, */
/* PLL enabled, */
/* SYSCLK=CPUCLK/2 */
SYSCR = 0x40c0;
}
/********************************************************** */
/* READ CAPTURE FIFO REGISTERS
/* This routine is used to read the data from the capture FIFO
/* registers.
/*
/* inputs: capture = which FIFO to read?
/* range = 1–3
/* outputs fifo_data =
/* range = 0–65535
/********************************************************* */
unsigned int read_fifo(int capture)
{
unsigned int fifo_data;
int fifo_status;
if (capture == 1)
{
do {
fifo_data = FIFO1; /* read value */
fifo_status = CAPFIFO & 0x0300; /* read status register, mask bits */
}
while (fifo_status != 0);
}
else if (capture == 2)
{
do {
fifo_data = FIFO2; /* read value */
fifo_status = CAPFIFO & 0x0c00; /* read status register, mask bits */
}
while (fifo_status != 0);
}
else if (capture == 3)
{
do {
fifo_data = FIFO3; /* read value */
fifo_status = CAPFIFO & 0x3000; /* read status register, mask bits */
}
while (fifo_status !=0);
}
else {
fifo_data = 0xffff; /* error, not a valid capture */
}
return fifo_data;
}
/* ISR for A/D and keyboard interrupt */
void c_int6()
{
unsigned int x1,x2,i,j;
unsigned int sysint_vector;
IFR=0x0020;
IMR=0x0000; /* Clear interrupt flags */
sysint_vector=SYSIVR; /* read interrupt vector address offset */
if (sysint_vector==0x0004) /* if ADC interrupt */
ADC_ISR();
else if (sysint_vector==0x0001)
{ /* if keyboard(XINT1) interrupt */
/*keyboard_ISR(); */
port0=0x7f;
x2=port5;
x1=x2 & 0x0f;
port1=0x00;
port2=0x0f;
port3=0x0f;
switch(x1)
{
case 0x0e:port4=0x04;
break;
case 0x0d:port4=0x03;
break;
case 0x0b:port4=0x02;
break;
case 0x07:port4=0x01;
break;
case 0x00:port4=0x00;
break;
case 0x0f:port4=0x05;
break;
default: port4=0x0f;
break;
}
XINT1CR=0x8007;
IMR = 0x0020;
IFR=0x0020;
}
}
/*******************************************************************/
void disable_interrupts()
{
asm(" SETC INTM");
}
/************************************************************************/
void enable_interrupts()
{
IMR = 0x0001; /* Enable CPU Interrupts:INT 1,2,3,4,6 */
IFR = 0xffff; /* Clear pending interrupts */
IFRA = 0xffff;
IFRB = 0xffff;
IFRC = 0xffff;
/*IMRA = 0x0085; /* Enable timer 1 period and PDPINT interrupts */
/*IMRB = 0x0010; /* Enable timer 3 period interrupts */
/*IMRC = 0x0007; /* Enable CAP1–CAP3 interrupts*/
asm(" CLRC INTM"); /* Global interrupt enable */
}
/* ***************************************************************** */
/* The main program
/* ***************************************************************** */
main()
{
unsigned int temp,x1,x2;
asm(" SETC INTM");
/*********************************************/
/* Disable watchdog timer */
/*********************************************/
temp = WDCR;
temp = temp|0x68;
WDCR = temp;
/*dsp_setup();
/*init_SRM(); */
/*eventmgr_init(); */
/*enable_interrupts(); */
XINT1CR=0x8007;
IMR = 0x0020; /* Enable CPU Interrupts:INT 1,2,3,4,6 */
IFR = 0xffff; /* Clear pending interrupts */
IFRA = 0xffff;
IFRB = 0xffff;
IFRC = 0xffff;
port2=0x00;
port3=0x10;
x1=0x00;
x2=0x01;
if (x1==0)
x2=0x02;
for(;;)
{port1=0x00;
/*x2=port5; */
/*x2=port5;
x1=x2 & 0x0f; */
switch(port5 & 0x0f)
{
case 0x0e : port4=0x04;
break;
case 0x0d : port4=0x03;
break;
case 0x0b : port4=0x02;
break;
case 0x07 : port2=0x00;
port3=0x10;
port4=0x01;
break;
case 0x00 : port4=0x00;
break;
case 0x0f : port4=0x05;
break;
default: port4=0x0f;
break;
}
}
port0=0xff;
/*IMRA = 0x0081; /* Enable timer 1 period and PDPINT interrupts */
/*IMRB = 0x0010; /* Enable timer 3 period interrupts */
/*IMRC = 0x0007; /* Enable CAP1–CAP3 interrupts*/
/*asm(" CLRC INTM"); /* Global interrupt enable */
for(;;)
{
port0=0x7f;
}
}
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -