📄 srm.c
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/* Initialize T2 */
T2PER=0x0320; /* Period is 20us */
T2CON=0x9040;
/* Setup shared pins */
OCRA = 0xf800; /* pins IOPB0–IOPB3 & IOPA0–IOPA2 to I/O pins */
OCRB = 0x00f1; /* pins are: ADSOC, XF, /BIO, CAP1–CAP4 */
PADATDIR = 0x0700; /* outputs IOPA0–IOPA2, set low */
PBDATDIR = 0x0707; /* outputs IOPB0–IOPB2, set high */
}
/********************************************************** */
/* READ CAPTURE FIFO REGISTERS
/* This routine is used to read the data from the capture FIFO
/* registers.
/*
/* inputs: capture = which FIFO to read?
/* range = 1–3
/* outputs fifo_data =
/* range = 0–65535
/********************************************************* */
unsigned int read_fifo(int capture)
{
unsigned int fifo_data;
int fifo_status;
if (capture == 1)
{
do {
fifo_data = FIFO1; /* read value */
fifo_status = CAPFIFO & 0x0300; /* read status register, mask bits */
}
while (fifo_status != 0);
}
else if (capture == 2)
{
do {
fifo_data = FIFO2; /* read value */
fifo_status = CAPFIFO & 0x0c00; /* read status register, mask bits */
}
while (fifo_status != 0);
}
else if (capture == 3)
{
do {
fifo_data = FIFO3; /* read value */
fifo_status = CAPFIFO & 0x3000; /* read status register, mask bits */
}
while (fifo_status !=0);
}
else {
fifo_data = 0xffff; /* error, not a valid capture */
}
return fifo_data;
}
/* ISR for GPT1,PDP interrupt */
void c_int2()
{
int groupa_flags;
IFR=0x0002; /* clear CPU interrupt flag */
groupa_flags=IFRA;
if (groupa_flags & 0x1) /* if PDP interrupt */
{
IFRA=0x077f; /* clear interrupt flag */
PADATDIR = 0x0007;
}
else if (groupa_flags & 0x80) /* if GPT1 interrupt */
{
IFRA=0x07fe; /* clear interrupt flag */
display_times++;
}
else
IFRA=0x7ff; /* not a valid interrupt */
}
/* ISR for GPT3 interrupt */
void c_int3()
{int groupa_flags;
IFR=0x0004; /* clear CPU interrupt flag */
groupa_flags=IFRB;
if (groupa_flags & 0x1) /* if GPT2 interrupt */
{
IFRB=0x07f; /* clear interrupt flag */
}
else if (groupa_flags & 0x80) /* if GPT3 interrupt */
{
IFRB=0x0fe; /* clear interrupt flag */
T3overflow_counter++;
}
else
IFRB=0x0ff; /* not a valid interrupt */
}
/* ISR for CAP unit interrupt */
void c_int4()
{
int groupc_flags;
int capture;
struct CAP_INT * p;
IFR=0x0008; /* clear CPU interrupt flag */
groupc_flags = IFRC; /* read event manger interrupt */
/* flag register */
if ((groupc_flags & 0x07)==0)
{
/* not a valid capture */
IFRC = 0xff;
capture = 0;
}
p=CAP_p;
CAP_p=CAP_p->next;
if (groupc_flags & 0x1)
{
/* capture #1 */
IFRC = 0xf9; /* clear flag register */
capture = 1;
if (CAP1_flag)
{
if (CAP_A)
CAP_A=0;
else
CAP_A=1;
PADATDIR=PAvalue[CAP_A];
}
}
else if (groupc_flags & 0x2)
{
/* capture #2 */
IFRC = 0xfa;
capture = 2;
CAP1_flag=TRUE;
if (CAP_B)
CAP_B=0;
else
CAP_B=1;
PADATDIR=PAvalue[CAP_B+2];
}
else if (groupc_flags & 0x4)
{
/* capture #3 */
IFRC = 0xfc;
capture = 3;
CAP1_flag=TRUE;
if (CAP_C)
CAP_C=0;
else
CAP_C=1;
PADATDIR=PAvalue[CAP_C+4];
}
CAP_p->CAP_value = read_fifo(capture); /* read FIFO */
CAP_p->delta_count=65536*T3overflow_counter+CAP_p->CAP_value-p->delta_count;
T3overflow_counter=0;
position=position+75; /* accumulate position */
}
/* ISR for A/D and keyboard interrupt */
void c_int6()
{
unsigned int sysint_vector;
IFR=0x0020; /* Clear interrupt flags */
sysint_vector=SYSIVR; /* read interrupt vector address offset */
if (sysint_vector=0x0004) /* if ADC interrupt */
{
ADCTRL1=ADCTRL1 | 0x100;
ADC_ISR();
}
else if (sysint_vector=0x0002) /* if keyboard(XINT1) interrupt */
keyboard_ISR();
}
/* initiating parameter and register */
void init_SRM()
{
velocity_value=0;
velocity_dotbit=4;
position_value=position=0;
position_dotbit=4;
input_value=0;
input_dotbit=4;
display_times=0;
display_order=1;
/* start ADC */
ADCTRL1=0xcb04;
ADCTRL2=0x0404;
ADC_channel=2;
}
/*******************************************************************/
void disable_interrupts()
{
asm(" SETC INTM");
}
/************************************************************************/
void enable_interrupts()
{
IFR = 0xffff; /* Clear pending interrupts */
IFRA = 0xffff;
IFRB = 0xffff;
IFRC = 0xffff;
IMR = 0x002e; /* Enable CPU Interrupts:INT 2,3,4,6 */
IMRA = 0x0081; /* Enable timer 1 period interrupts */
IMRB = 0x0081; /* Enable timer 2 period and temer 3 upflow interrupts */
IMRC = 0x0007; /* Enable CAP1–CAP3 interrupts*/
asm(" CLRC INTM"); /* Global interrupt enable */
}
/* display data on LCD */
void display(display_value,dot_bit)
unsigned int display_value; /* the value want to be displayed */
int dot_bit; /* dot bit */
{
unsigned int bit_value[4];
int x;
port1=0;
if (display_value>=2000)
port1=port1|0x40;
bit_value[3]=display_value%10; /* the lowest bit data */
bit_value[2]=(display_value/10)%10;
bit_value[1]=(display_value/100)%10;
bit_value[0]=display_value/1000; /* the highest bit data */
if (bit_value[0]==1)
port1=port1|0x02;
if (sign_state)
port1=port1|0x01;
x=dot_bit;
if (x!=4)
port1=port1|(1<<(x+1)); /* show radix point */
port2=bit_value[1];
port3=bit_value[2];
port4=bit_value[3];
if ((dot_bit==3)&&(bit_value[1]==0)&&(bit_value[0]==0))
port3=0x0f;
}
/* ***************************************************************** */
/* The main program
/* ***************************************************************** */
main()
{
unsigned int velocity;
disable_interrupts();
dsp_setup();
init_SRM();
eventmgr_init();
enable_interrupts();
for(;;)
{
if (display_times>=250)
{
display_times=0;
switch(display_order)
{
case 1: /* read velocity */
if (CAP_p->delta_count==0)
velocity=0;
else
velocity=VELOCITY_CONST*10/CAP_p->delta_count;
velocity_value=velocity;
if (velocity_value%10)
{
velocity_value=velocity;
velocity_dotbit=3;
if (velocity_value>2000)
{
velocity_value=velocity/10;
velocity_dotbit=4;
}
}
else
{
velocity_value=velocity;
velocity_dotbit=4;
}
display(velocity_value,velocity_dotbit); break;
case 2: /* read position */
position_value=position;
if (position_value%10)
{
position_value=position;
position_dotbit=3;
if (position_value>2000)
{
position_value=position/10;
position_dotbit=4;
}
}
else
{
position_value=position;
position_dotbit=4;
}
display(position_value,position_dotbit); break;
case 3: display(input_value,input_dotbit); break;
default: break;
}
}
}
}
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