📄 main1.c
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#include "C240.h"
/* define constant value */
#define FALSE 0
#define TRUE 1
#define VELOCITY_CONST 1562500
/* define variable */
unsigned int IA_max,IB_max,IC_max; /* MAX limit for current */
unsigned int IA_min,IB_min,IC_min; /* MIN limit for current */
unsigned int ADC_channel; /* Channel for A/D convert */
int display_times; /* accumulation for display */
int T3overflow_counter; /* T3 overflow times */
int input_state;
int sign_state;
int dot_state;
int CAP1_flag;
int inputdata_num;
unsigned int input_value;
unsigned int input_dotbit;
unsigned int position_value;
unsigned int position_dotbit;
unsigned int position;
unsigned int velocity_value;
unsigned int velocity_dotbit;
unsigned int int_position;
int display_order; /* 1 while display velocity ,2 while display current ,3 while display input data */
/* define Input/Output variable value */
ioport unsigned int port0,port1,port2,port3,port4;
/* define structure type and variable value */
struct CAP_INT
{
unsigned int PA_value;
unsigned int CAP_value;
long delta_count;
struct CAP_INT * next;
};
struct CAP_INT * CAP_p;
/*********************************************/
/* Creat circle linkage table */
struct CAP_INT * creat_link()
{
int i;
struct CAP_INT * h,* p; /* pointer h point to virtual value */
h=(struct CAP_INT *)malloc(sizeof(struct CAP_INT));
h->next=h;
for(i=1;i<=6;i++)
{
p=(struct CAP_INT *)malloc(sizeof(struct CAP_INT));
p->PA_value=0;
p->CAP_value=0;
p->delta_count=0;
p->next=h->next;
h->next=p;
}
return (h); /* return head pointer */
}
/* stop SRM */
void SRM_stop(stop_phase,stop_position,stop_sign)
int stop_phase,stop_sign;
unsigned int stop_position;
{
static int phase1[16]={0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
static int phase2[16]={0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
CAPCON=0x0600;
if (stop_sign)
switch(stop_position)
{case 1:IA_max=phase1[stop_position];
IC_max=phase2[stop_position];
PADATDIR=0x0705;
case 2:IC_max=phase1[stop_position];
IB_max=phase2[stop_position];
PADATDIR=0x0706;
case 3:IB_max=phase1[stop_position];
IA_max=phase2[stop_position];
PADATDIR=0x0703;
}
else
switch(stop_position)
{case 1:IA_max=phase1[stop_position];
IB_max=phase2[stop_position];
PADATDIR=0x0703;
case 2:IB_max=phase1[stop_position];
IC_max=phase2[stop_position];
PADATDIR=0x0706;
case 3:IC_max=phase1[stop_position];
IA_max=phase2[stop_position];
PADATDIR=0x0705;
}
}
/*********************************************/
void ADC_ISR()
{
unsigned int x1,x2,channel,I_MAX,I_MIN;
x1=ADCTRL1|0x010e;
if (ADC_channel>4)
ADC_channel=2;
channel=ADC_channel;
x2=x1&ADC_channel; /* ADC_channel=2,3,4 */
ADCTRL1=x2;
ADCTRL2=0x0404; /* Start A/D convert for next channel */
x1=ADCFIFO1;
x2=x1>>6;
switch(channel)
{
case 2:I_MAX=IA_max;
I_MIN=IA_min;
case 3:I_MAX=IB_max;
I_MIN=IB_min;
case 4:I_MAX=IC_max;
I_MIN=IC_min;
default:break;
}
if (x2>=I_MAX)
{
x1=PBDATDIR&(~(1<<(ADC_channel-2)));
PBDATDIR=x1;
}
if (x2<=I_MIN)
{
x1=PBDATDIR|(1<<(ADC_channel-2));
PBDATDIR=x1;
}
ADC_channel++;
}
/*********************************************/
void keyboard_ISR()
{
int i;
static unsigned int clock_PAvalue[6]={0x0706,0x0702,0x0703,0x0701,0x0705,0x0704};
static unsigned int anticlock_PAvalue[6]={0x0706,0x0704,0x0705,0x0701,0x0703,0x0702};
struct CAP_INT * p;
unsigned int scan_in,scan_out;
int row,column=0,key_NO; /* row=0,1,2; column=1,2,3,4 */
row=0;
scan_out=0x0e;
port0=scan_out; /* scan keyboard */
scan_in=port1;
while ((scan_in&0x0f)==0x0f)
{
port0=scan_out<<1;
scan_in=port1;
row++;
if (row>=4)
{
row=17;
break;
}
}
switch(scan_in & 0x0f)
{
case 0x0e: column=1;
break;
case 0x0d: column=2;
break;
case 0x0b: column=3;
break;
case 0x07: column=4;
break;
default : column=17;
}
/* for(;;)
{
scan_in=port1;
if ((scan_in & 0x0f)==0x0f)
break;
} */
key_NO=4*row+column;
switch(key_NO)
{
case 1 :
case 2 :
case 3 :
case 4 :
case 5 :
case 6 :
case 7 :
case 8 :
case 9 :
case 10 : if (input_state==FALSE) /* deal with data keyboard */
break;
if (dot_state)
input_dotbit--;
input_value=input_value*10+key_NO-1;
inputdata_num++;
break;
case 11 : if (input_state==FALSE) /* deal with radix point keyboard */
break;
if (dot_state)
break;
input_dotbit=3;
if ((input_dotbit==0) || (inputdata_num>=4))
input_dotbit=4;
break;
case 12 : if (sign_state) /* deal with sign keyboard */
sign_state=FALSE;
else
sign_state=TRUE;
break;
/***********************/
/* code for denote the reverse state */
/***********************/
case 13 : /*PADATDIR = 0x0702; /* fire phase B */
input_state=TRUE;
sign_state=FALSE;
dot_state=FALSE;
display_order=3;
inputdata_num=0;
/* location SRM, fire phase A */
PADATDIR = 0x0701; /* outputs IOPA0–IOPA2, IOPA0 set high */
break;
case 14 : display_order++;
if (display_order==4);
display_order=1;
break;
case 15 : display_order=1;
CAP1_flag=FALSE;
position_value=position=0;
position_dotbit=4;
/* Setup capture units */
CAPCON = 0x0; /* reset capture control register */
CAPFIFO= 0x00ff; /* Clear FIFO’s */
/* Initialize T3 */
T3CNT=0x0;
T3PER=0xffff;
CAPCON = 0xb6fc; /* enable #1–3, use Timer3, both edges */
/* start CAP */
T3CON=0x9440; /* Prescaler=/16 */
/* initiate link->PA_value */
CAP_p=creat_link();
p=CAP_p->next;
if (sign_state) /* drive SRM */
{
PADATDIR=0x0702;
for(i=0;i<=5;i++)
{
p->PA_value=anticlock_PAvalue[i];
p->delta_count=0;
p=p->next;
}
}
else
{
PADATDIR=0x0704;
for(i=0;i<=5;i++)
{
p->PA_value=clock_PAvalue[i];
p->delta_count=0;
p=p->next;
}
}
input_state=FALSE;
T3overflow_counter=0;
/* handle position */
int_position=input_value;
if (input_dotbit>0&&input_dotbit<4)
for(i=1;i<=(4-input_dotbit);i++)
int_position=int_position/10;
if (int_position<=15)
/* disable CAP */
SRM_stop(3,int_position,sign_state);
else
break;
case 16 :
/* stop SRM */
CAPCON=0x0600;
PADATDIR = 0x0701; /* outputs IOPA0–IOPA2, IOPA0 set high */
default : break;
}
}
/*********************************************/
void dsp_setup()
{
unsigned int temp;
/*********************************************/
/* Disable watchdog timer */
/*********************************************/
temp = WDCR;
temp = temp|0x68;
WDCR = temp;
/*********************************************/
/* initialize PLL module (20 MHz XTAL1) */
/*********************************************/
CKCR1 = 0x61; /* crystal=20MHz CPUCLK = 40MHz */
/* and 2x PLL mult ratio */
CKCR0 = 0xc3; /* low–power mode 0, */
/* ACLK enabled, */
/* PLL enabled, */
/* SYSCLK=CPUCLK/2 */
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