📄 memory_mb411.s
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/*
* File : memory_mb411stb7100.S
* Synopsys : Sample memory configuration for mb411 (STb7100)
*
* Copyright 2005, 2006 STMicroelectronics Limited. All right reserved.
*
* Provides __memory_setup_table which describes how to
* program up the LMI and EMI.
*
* This table was manually derrived from the GDB
* configure scripts.
*/
#define _SH4REG_ASM_
#include <boardreg.h>
/*
* Default to 27MHz external clock source.
*/
#ifndef MB411STB7100EXTCLK
#define MB411STB7100EXTCLK 27
#endif
.section .text
.org 0x0
.global __memory_setup_table
.global __memory_setup_table_end
.global _led_on
.global _led_off
/*
* Routines to switch an LED on and off on this platform.
*/
_led_off:
bra 1f
mov #1, r0
_led_on:
mov #0, r0
1: mov.l led_addr, r1
rts
mov.b r0, @r1
.balign 4
led_addr:
.long 0xa2100010
/*
* The poke table is a series of long words, in the format
*
* opcode, address, operand, ...
*
* An opcode of 0 marks the table end
*/
#define POKE_UPDATE_LONG(A1, A2, AND, SHIFT, OR) .long 8, A1, A2, AND, SHIFT, OR
#define WHILE_NE(A, AND, VAL) .long 7, A, AND, VAL
#define UPDATE_LONG(A, AND, OR) .long 6, A, AND, OR
#define OR_LONG(A, V) .long 5, A, V
#define POKE_LONG(A, V) .long 4, A, V
#define POKE_SHORT(A, V) .long 2, A, V
#define POKE_CHAR(A, V) .long 1, A, V
#define END_MARKER .long 0, 0, 0
.balign 4
__memory_setup_table:
#ifdef PREPOKEINCLUDE
#include PREPOKEINCLUDE
#endif
/*
* CLOCKGENA setup PLL0
*/
POKE_LONG(STB7100_CLOCKGENA_LOCK, 0xc0de)
OR_LONG(STB7100_CLOCKGENA_PLL0_CFG, 0x00100000)
UPDATE_LONG(STB7100_CLOCKGENA_PLL0_CFG, 0xfff7ffff, 0)
#if MB411STB7100EXTCLK == 30
UPDATE_LONG(STB7100_CLOCKGENA_PLL0_CFG, 0xfff80000, 0x14 | (0xb1 << 8) | (0x0 << 16))
#elif MB411STB7100EXTCLK == 27
UPDATE_LONG(STB7100_CLOCKGENA_PLL0_CFG, 0xfff80000, 0x06 | (0x3b << 8) | (0x0 << 16))
#else
#error Unsupported external clock frequency
#endif
OR_LONG(STB7100_CLOCKGENA_PLL0_CFG, 0x00080000)
WHILE_NE(STB7100_CLOCKGENA_PLL0_STATUS, 0x00000001, 0x00000001)
UPDATE_LONG(STB7100_CLOCKGENA_PLL0_CFG, 0xffefffff, 0)
POKE_LONG(STB7100_CLOCKGENA_LOCK, 0x0)
/*
* CLOCKGENA setup PLL1
*/
POKE_LONG(STB7100_CLOCKGENA_LOCK, 0xc0de)
POKE_LONG(STB7100_CLOCKGENA_PLL1_BYPASS, 0x00000002)
UPDATE_LONG(STB7100_CLOCKGENA_PLL1_CFG, 0xfff7ffff, 0)
#if MB411STB7100EXTCLK == 30
UPDATE_LONG(STB7100_CLOCKGENA_PLL1_CFG, 0xfff80000, 0x1e | (0xc8 << 8) | (0x0 << 16))
#elif MB411STB7100EXTCLK == 27
UPDATE_LONG(STB7100_CLOCKGENA_PLL1_CFG, 0xfff80000, 0x1b | (0xc8 << 8) | (0x0 << 16))
#else
#error Unsupported external clock frequency
#endif
OR_LONG(STB7100_CLOCKGENA_PLL1_CFG, 0x00080000)
WHILE_NE(STB7100_CLOCKGENA_PLL1_STATUS, 0x00000001, 0x00000001)
POKE_LONG(STB7100_CLOCKGENA_PLL1_BYPASS, 0x00000000)
POKE_LONG(STB7100_CLOCKGENA_LOCK, 0x0)
/*
* SYSCONF setup
*/
POKE_LONG(STB7100_SYSCONF_SYS_CFG11, 0x0d7f80c0)
WHILE_NE(STB7100_SYSCONF_SYS_STA12, (1 << 9) | (1 << 19), (1 << 9) | (1 << 19))
WHILE_NE(STB7100_SYSCONF_SYS_STA13, (1 << 9) | (1 << 19), (1 << 9) | (1 << 19))
POKE_LONG(STB7100_SYSCONF_SYS_CFG12, 0x4000000f | (0xf << 12) | (0xf << 23))
POKE_LONG(STB7100_SYSCONF_SYS_CFG13, 0x4000000f | (0xf << 12) | (0xf << 23))
POKE_LONG(STB7100_STBUS_NODE04_N02_PRIORITY, 0x1)
/*
* LMI SYS setup
*/
POKE_LONG(ST40_LMI_MIM_0(SYS), 0x861a025f)
POKE_LONG(ST40_LMI_MIM_1(SYS), 0x01010022)
POKE_LONG(ST40_LMI_STR_0(SYS), 0x35b06455)
POKE_LONG(ST40_LMI_SDRA0_0(SYS), 0x08001900)
POKE_LONG(ST40_LMI_SDRA1_0(SYS), 0x08001900)
POKE_LONG(ST40_LMI_SCR_0(SYS), 0x00000001)
POKE_LONG(ST40_LMI_SCR_0(SYS), 0x00000003)
POKE_LONG(ST40_LMI_SCR_0(SYS), 0x00000001)
POKE_LONG(ST40_LMI_SCR_0(SYS), 0x00000002)
POKE_LONG(ST40_LMI_SDMR0(SYS), 0x00000402)
POKE_LONG(ST40_LMI_SDMR0(SYS), 0x00000133)
POKE_LONG(ST40_LMI_SCR_0(SYS), 0x00000002)
POKE_LONG(ST40_LMI_SCR_0(SYS), 0x00000004)
POKE_LONG(ST40_LMI_SCR_0(SYS), 0x00000004)
POKE_LONG(ST40_LMI_SCR_0(SYS), 0x00000004)
POKE_LONG(ST40_LMI_SDMR0(SYS), 0x00000033)
POKE_LONG(ST40_LMI_SCR_0(SYS), 0x00000000)
/*
* LMI VID setup
*/
POKE_LONG(ST40_LMI_MIM_0(VID), 0x861a025f)
POKE_LONG(ST40_LMI_MIM_1(VID), 0x01010022)
POKE_LONG(ST40_LMI_STR_0(VID), 0x35b06455)
POKE_LONG(ST40_LMI_SDRA0_0(VID), 0x14001900)
POKE_LONG(ST40_LMI_SDRA1_0(VID), 0x14001900)
POKE_LONG(ST40_LMI_SCR_0(VID), 0x00000001)
POKE_LONG(ST40_LMI_SCR_0(VID), 0x00000003)
POKE_LONG(ST40_LMI_SCR_0(VID), 0x00000001)
POKE_LONG(ST40_LMI_SCR_0(VID), 0x00000002)
POKE_LONG(ST40_LMI_SDMR0(VID), 0x00000402)
POKE_LONG(ST40_LMI_SDMR0(VID), 0x00000133)
POKE_LONG(ST40_LMI_SCR_0(VID), 0x00000002)
POKE_LONG(ST40_LMI_SCR_0(VID), 0x00000004)
POKE_LONG(ST40_LMI_SCR_0(VID), 0x00000004)
POKE_LONG(ST40_LMI_SCR_0(VID), 0x00000004)
POKE_LONG(ST40_LMI_SDMR0(VID), 0x00000033)
POKE_LONG(ST40_LMI_SCR_0(VID), 0x00000000)
/*
* EMI setup
*/
POKE_LONG(ST40_EMI_BANK_ENABLE, 0x00000005)
POKE_LONG(ST40_EMI_BANK0_BASEADDRESS, 0x00000000)
POKE_LONG(ST40_EMI_BANK1_BASEADDRESS, 0x00000004)
POKE_LONG(ST40_EMI_BANK2_BASEADDRESS, 0x00000008)
POKE_LONG(ST40_EMI_BANK3_BASEADDRESS, 0x0000000a)
POKE_LONG(ST40_EMI_BANK4_BASEADDRESS, 0x0000000c)
POKE_LONG(ST40_EMI_BANK0_EMICONFIGDATA0, 0x001016d1)
POKE_LONG(ST40_EMI_BANK0_EMICONFIGDATA1, 0x9d200000)
POKE_LONG(ST40_EMI_BANK0_EMICONFIGDATA2, 0x9d220000)
POKE_LONG(ST40_EMI_BANK0_EMICONFIGDATA3, 0x00000000)
POKE_LONG(ST40_EMI_BANK2_EMICONFIGDATA0, 0x002046f9)
POKE_LONG(ST40_EMI_BANK2_EMICONFIGDATA1, 0xa5a00000)
POKE_LONG(ST40_EMI_BANK2_EMICONFIGDATA2, 0xa5a20000)
POKE_LONG(ST40_EMI_BANK2_EMICONFIGDATA3, 0x00000000)
POKE_LONG(ST40_EMI_BANK3_EMICONFIGDATA0, 0x00200791)
POKE_LONG(ST40_EMI_BANK3_EMICONFIGDATA1, 0x0c006700)
POKE_LONG(ST40_EMI_BANK3_EMICONFIGDATA2, 0x0c006700)
POKE_LONG(ST40_EMI_BANK3_EMICONFIGDATA3, 0x00000000)
POKE_LONG(ST40_EMI_BANK4_EMICONFIGDATA0, 0x042086f1)
POKE_LONG(ST40_EMI_BANK4_EMICONFIGDATA1, 0x88112111)
POKE_LONG(ST40_EMI_BANK4_EMICONFIGDATA2, 0x88112211)
POKE_LONG(ST40_EMI_BANK4_EMICONFIGDATA3, 0x00000000)
POKE_LONG(ST40_EMI_GENCFG, 0x00000050)
#ifdef POSTPOKEINCLUDE
#include POSTPOKEINCLUDE
#endif
END_MARKER
__memory_setup_table_end:
.end
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