memory_mb411stb7109.s

采用ST20 CPU的机顶盒的烧写程序

	POKE_LONG(ST40_EMI_BANK_ENABLE, 0x00000005)
	POKE_LONG(ST40_EMI_BANK0_BASEADDRESS, 0x00000000)
	POKE_LONG(ST40_EMI_BANK1_BASEADDRESS, 0x00000004)
	POKE_LONG(ST40_EMI_BANK2_BASEADDRESS, 0x00000008)
	POKE_LONG(ST40_EMI_BANK3_BASEADDRESS, 0x0000000a)
	POKE_LONG(ST40_EMI_BANK4_BASEADDRESS, 0x0000000c)
	POKE_LONG(ST40_EMI_BANK0_EMICONFIGDATA0, 0x001016d1)
	POKE_LONG(ST40_EMI_BANK0_EMICONFIGDATA1, 0x9d200000)
	POKE_LONG(ST40_EMI_BANK0_EMICONFIGDATA2, 0x9d220000)
	POKE_LONG(ST40_EMI_BANK0_EMICONFIGDATA3, 0x00000000)
	POKE_LONG(ST40_EMI_BANK2_EMICONFIGDATA0, 0x002046f9)
	POKE_LONG(ST40_EMI_BANK2_EMICONFIGDATA1, 0xa5a00000)
	POKE_LONG(ST40_EMI_BANK2_EMICONFIGDATA2, 0xa5a20000)
	POKE_LONG(ST40_EMI_BANK2_EMICONFIGDATA3, 0x00000000)
	POKE_LONG(ST40_EMI_BANK3_EMICONFIGDATA0, 0x00200791)
	POKE_LONG(ST40_EMI_BANK3_EMICONFIGDATA1, 0x0c006700)
	POKE_LONG(ST40_EMI_BANK3_EMICONFIGDATA2, 0x0c006700)
	POKE_LONG(ST40_EMI_BANK3_EMICONFIGDATA3, 0x00000000)
	POKE_LONG(ST40_EMI_BANK4_EMICONFIGDATA0, 0x042086f1)
	POKE_LONG(ST40_EMI_BANK4_EMICONFIGDATA1, 0x88112111)
	POKE_LONG(ST40_EMI_BANK4_EMICONFIGDATA2, 0x88112211)
	POKE_LONG(ST40_EMI_BANK4_EMICONFIGDATA3, 0x00000000)
	POKE_LONG(ST40_EMI_GENCFG, 0x00000010)

#ifdef POSTPOKEINCLUDE
#include POSTPOKEINCLUDE
#endif

	END_MARKER

__memory_setup_table_end:

#ifdef SE_MODE_BOOTSTRAP

/* Macros which can be used to set particular SE mode PMB configurations */
#define SE_MODE_DEFAULT  1
#define SE_MODE_UNCACHED 2
#define SE_MODE_29BIT    3

#if (SE_MODE_BOOTSTRAP != SE_MODE_29BIT)
/*
 * In the default case the PMBs are setup as follows:
 *  - SYS RAM mapped at 0x80000000 (uncached if SE_MODE_UNCACHED)
 *  - VID RAM mapped at 0xa0000000 (uncached if SE_MODE_UNCACHED)
 *  - P2 from 0xB8000000 mapped as uncacheable mapping of 0x18000000 to
 *    0x1c000000 to cover the peripheral area
 *
 * Note that we also need to manually move the System and Video LMI base
 * addresses to their 32-bit SE mode locations as defined in the datasheet.
 */
__pmb_setup_table:
        UPDATE_LONG(STB7109_SYSCONF_SYS_CFG36, 0xFF00FF00, 0x00600040)
        POKE_LONG(ST40_LMI_SDRA0_0(SYS), 0x44001900)
        POKE_LONG(ST40_LMI_SDRA1_0(SYS), 0x44001900)
        POKE_LONG(ST40_LMI_SDRA0_0(VID), 0x64001900)
        POKE_LONG(ST40_LMI_SDRA1_0(VID), 0x64001900)

        POKE_LONG(SH4_PMB_ADDR_ARRAY_ENTRY(0), 0x80000000) /* Virtual address */
        POKE_LONG(SH4_PMB_DATA_ARRAY_ENTRY(0), (1 << 8) |  /* Valid */
#if (SE_MODE_BOOTSTRAP != SE_MODE_UNCACHED)
                                               (1 << 3) |  /* Cacheable */
#endif /* (SE_MODE_BOOTSTRAP != SE_MODE_UNCACHED) */
                                               0x10     |  /* 64MB page size */
                                               0x40000000) /* Physical address */

        POKE_LONG(SH4_PMB_ADDR_ARRAY_ENTRY(1), 0xa0000000) /* Virtual address */
        POKE_LONG(SH4_PMB_DATA_ARRAY_ENTRY(1), (1 << 8) |  /* Valid */
#if (SE_MODE_BOOTSTRAP != SE_MODE_UNCACHED)
                                               (1 << 3) |  /* Cacheable */
#endif /* (SE_MODE_BOOTSTRAP != SE_MODE_UNCACHED) */
                                               0x10     |  /* 64MB page size */
                                               0x60000000) /* Physical address */

        POKE_LONG(SH4_PMB_ADDR_ARRAY_ENTRY(2), 0xb8000000) /* Virtual address */
        POKE_LONG(SH4_PMB_DATA_ARRAY_ENTRY(2), 0x10     |  /* 64MB page size */
                                               (1 << 8) |  /* Valid */
                                               0x18000000) /* Physical address */
#if STB7109_MOVE_LMI_REGS
        POKE_LONG(SH4_PMB_ADDR_ARRAY_ENTRY(3), 0)
        POKE_LONG(SH4_PMB_DATA_ARRAY_ENTRY(3), 0)
        POKE_LONG(SH4_PMB_ADDR_ARRAY_ENTRY(4), 0)
        POKE_LONG(SH4_PMB_DATA_ARRAY_ENTRY(4), 0)
#else
        POKE_LONG(SH4_PMB_ADDR_ARRAY_ENTRY(3), 0xaf000000) /* Virtual address */
        POKE_LONG(SH4_PMB_DATA_ARRAY_ENTRY(3), 0x00     |  /* 16MB page size */
                                               (1 << 8) |  /* Valid */
                                               0x0f000000) /* Physical address */
        POKE_LONG(SH4_PMB_ADDR_ARRAY_ENTRY(4), 0xb7000000) /* Virtual address */
        POKE_LONG(SH4_PMB_DATA_ARRAY_ENTRY(4), 0x00     |  /* 16MB page size */
                                               (1 << 8) |  /* Valid */
                                               0x17000000) /* Physical address */
#endif
        /* Clear remaining entries */
        POKE_LONG(SH4_PMB_ADDR_ARRAY_ENTRY(5), 0)
        POKE_LONG(SH4_PMB_DATA_ARRAY_ENTRY(5), 0)
        POKE_LONG(SH4_PMB_ADDR_ARRAY_ENTRY(6), 0)
        POKE_LONG(SH4_PMB_DATA_ARRAY_ENTRY(6), 0)
        POKE_LONG(SH4_PMB_ADDR_ARRAY_ENTRY(7), 0)
        POKE_LONG(SH4_PMB_DATA_ARRAY_ENTRY(7), 0)
        POKE_LONG(SH4_PMB_ADDR_ARRAY_ENTRY(8), 0)
        POKE_LONG(SH4_PMB_DATA_ARRAY_ENTRY(8), 0)
        POKE_LONG(SH4_PMB_ADDR_ARRAY_ENTRY(9), 0)
        POKE_LONG(SH4_PMB_DATA_ARRAY_ENTRY(9), 0)
        POKE_LONG(SH4_PMB_ADDR_ARRAY_ENTRY(10), 0)
        POKE_LONG(SH4_PMB_DATA_ARRAY_ENTRY(10), 0)
        POKE_LONG(SH4_PMB_ADDR_ARRAY_ENTRY(11), 0)
        POKE_LONG(SH4_PMB_DATA_ARRAY_ENTRY(11), 0)
        POKE_LONG(SH4_PMB_ADDR_ARRAY_ENTRY(12), 0)
        POKE_LONG(SH4_PMB_DATA_ARRAY_ENTRY(12), 0)
        POKE_LONG(SH4_PMB_ADDR_ARRAY_ENTRY(13), 0)
        POKE_LONG(SH4_PMB_DATA_ARRAY_ENTRY(13), 0)
        POKE_LONG(SH4_PMB_ADDR_ARRAY_ENTRY(14), 0)
        POKE_LONG(SH4_PMB_DATA_ARRAY_ENTRY(14), 0)
        POKE_LONG(SH4_PMB_ADDR_ARRAY_ENTRY(15), 0)
        POKE_LONG(SH4_PMB_DATA_ARRAY_ENTRY(15), 0)
        END_MARKER

#else /* (SE_MODE_BOOTSTRAP == SE_MODE_29BIT) */

/*
 * In the 29-bit compatibility mode case the PMBs are setup as follows:
 *  - P1 as cached RAM mapping (64MB sys followed by 64MB vid)
 *  - P2 as similar uncached RAM mapping
 *  - P2 from 0xB8000000 mapped as uncacheable mapping of 0x18000000 to
 *    0x1c000000 to cover the peripheral area
 *
 * Note that we also need to manually move the System and Video LMI base
 * addresses to their 32-bit SE mode locations as defined in the datasheet and
 * change the 'upper bound addresses' (in row attribute registers) for the LMIs.
 */
__pmb_setup_table:
        UPDATE_LONG(STB7109_SYSCONF_SYS_CFG36, 0xFF00FF00, 0x00600040)
        POKE_LONG(ST40_LMI_SDRA0_0(SYS), 0x44001900)
        POKE_LONG(ST40_LMI_SDRA1_0(SYS), 0x44001900)
        POKE_LONG(ST40_LMI_SDRA0_0(VID), 0x64001900)
        POKE_LONG(ST40_LMI_SDRA1_0(VID), 0x64001900)

        POKE_LONG(SH4_PMB_ADDR_ARRAY_ENTRY(0), 0x80000000) /* Virtual address */
        POKE_LONG(SH4_PMB_DATA_ARRAY_ENTRY(0), (1 << 3) |  /* Cacheable */
                                               0x10     |  /* 64MB page size */
                                               (1 << 8) |  /* Valid */
                                               0x40000000) /* Physical address */

        POKE_LONG(SH4_PMB_ADDR_ARRAY_ENTRY(1), 0x84000000) /* Virtual address */
        POKE_LONG(SH4_PMB_DATA_ARRAY_ENTRY(1), (1 << 3) |  /* Cacheable */
                                               0x10     |  /* 64MB page size */
                                               (1 << 8) |  /* Valid */
                                               0x60000000) /* Physical address */

        POKE_LONG(SH4_PMB_ADDR_ARRAY_ENTRY(2), 0xa0000000) /* Virtual address */
        POKE_LONG(SH4_PMB_DATA_ARRAY_ENTRY(2), 0x10     |  /* 64MB page size */
                                               (1 << 8) |  /* Valid */
                                               0x40000000) /* Physical address */

        POKE_LONG(SH4_PMB_ADDR_ARRAY_ENTRY(3), 0xa4000000) /* Virtual address */
        POKE_LONG(SH4_PMB_DATA_ARRAY_ENTRY(3), 0x10     |  /* 64MB page size */
                                               (1 << 8) |  /* Valid */
                                               0x60000000) /* Physical address */

        POKE_LONG(SH4_PMB_ADDR_ARRAY_ENTRY(4), 0xb8000000) /* Virtual address */
        POKE_LONG(SH4_PMB_DATA_ARRAY_ENTRY(4), 0x10     |  /* 64MB page size */
                                               (1 << 8) |  /* Valid */
                                               0x18000000) /* Physical address */
#if STB7109_MOVE_LMI_REGS
        POKE_LONG(SH4_PMB_ADDR_ARRAY_ENTRY(5), 0)
        POKE_LONG(SH4_PMB_DATA_ARRAY_ENTRY(5), 0)
        POKE_LONG(SH4_PMB_ADDR_ARRAY_ENTRY(6), 0)
        POKE_LONG(SH4_PMB_DATA_ARRAY_ENTRY(6), 0)
#else
        POKE_LONG(SH4_PMB_ADDR_ARRAY_ENTRY(5), 0xaf000000) /* Virtual address */
        POKE_LONG(SH4_PMB_DATA_ARRAY_ENTRY(5), 0x00     |  /* 16MB page size */
                                               (1 << 8) |  /* Valid */
                                               0x0f000000) /* Physical address */
        POKE_LONG(SH4_PMB_ADDR_ARRAY_ENTRY(6), 0xb7000000) /* Virtual address */
        POKE_LONG(SH4_PMB_DATA_ARRAY_ENTRY(6), 0x00     |  /* 16MB page size */
                                               (1 << 8) |  /* Valid */
                                               0x17000000) /* Physical address */
#endif
        /* Clear remaining entries */
        POKE_LONG(SH4_PMB_ADDR_ARRAY_ENTRY(7), 0)
        POKE_LONG(SH4_PMB_DATA_ARRAY_ENTRY(7), 0)
        POKE_LONG(SH4_PMB_ADDR_ARRAY_ENTRY(8), 0)
        POKE_LONG(SH4_PMB_DATA_ARRAY_ENTRY(8), 0)
        POKE_LONG(SH4_PMB_ADDR_ARRAY_ENTRY(9), 0)
        POKE_LONG(SH4_PMB_DATA_ARRAY_ENTRY(9), 0)
        POKE_LONG(SH4_PMB_ADDR_ARRAY_ENTRY(10), 0)
        POKE_LONG(SH4_PMB_DATA_ARRAY_ENTRY(10), 0)
        POKE_LONG(SH4_PMB_ADDR_ARRAY_ENTRY(11), 0)
        POKE_LONG(SH4_PMB_DATA_ARRAY_ENTRY(11), 0)
        POKE_LONG(SH4_PMB_ADDR_ARRAY_ENTRY(12), 0)
        POKE_LONG(SH4_PMB_DATA_ARRAY_ENTRY(12), 0)
        POKE_LONG(SH4_PMB_ADDR_ARRAY_ENTRY(13), 0)
        POKE_LONG(SH4_PMB_DATA_ARRAY_ENTRY(13), 0)
        POKE_LONG(SH4_PMB_ADDR_ARRAY_ENTRY(14), 0)
        POKE_LONG(SH4_PMB_DATA_ARRAY_ENTRY(14), 0)
        POKE_LONG(SH4_PMB_ADDR_ARRAY_ENTRY(15), 0)
        POKE_LONG(SH4_PMB_DATA_ARRAY_ENTRY(15), 0)
        END_MARKER

#endif /* (SE_MODE_BOOTSTRAP == SE_MODE_29BIT) */
#endif /* SE_MODE_BOOTSTRAP */

	.end