memory_mb411stb7109.s

采用ST20 CPU的机顶盒的烧写程序

/*
 * File     : memory_mb411stb7109.S
 * Synopsys : Sample memory configuration for mb411 (STb7109)
 *
 * Copyright 2005, 2006 STMicroelectronics Limited.  All right reserved.
 *
 * Provides __memory_setup_table which describes how to program up the LMI and
 * EMI.
 *
 * This table was manually derived from the GDB configure scripts.
 */
#define _SH4REG_ASM_
#include <boardreg.h>

/*
 * Default to 27MHz external clock source.
 */
#ifndef MB411STB7109EXTCLK
#define MB411STB7109EXTCLK 27
#endif

/*
 * Default to moving the LMI configuration registers.
 */
#ifndef STB7109_MOVE_LMI_REGS
#define STB7109_MOVE_LMI_REGS 1
#endif

	.section .text
	.org 0x0
	.global __memory_setup_table
	.global __memory_setup_table_end
	.global __pmb_setup_table
	.global _led_on
	.global _led_off

/*
 * Routines to switch an LED on and off on this platform.
 */
_led_off:
	bra	1f
	  mov	#1, r0

_led_on:
	mov	#0, r0

1:	mov.l	led_addr, r1
#ifdef SE_MODE_BOOTSTRAP
        mov.l   mmucr, r2
        mov.l   @r2, r3
        mov     #0x10, r4
        tst     r4, r3
        bt      1f
        
        /* SE mode is on!  As we are on a 7109 we know nothing is PMB mapped
         * above the identity area 6 mapping, so we map the top 16MB to cover
         * the LED register.
         */
        mov.l   led2, r1
        mov.l   pmb_a, r2
        mov.l   @r2, r3
        mov     #1, r4
        shll8   r4
        tst     r4, r3
        bf      1f
        mov.l   v_a, r3
        mov.l   r3, @r2
        mov.l   pmb_d, r2
        mov.l   p_a, r3
        mov.l   r3, @r2
#endif /* SE_MODE_BOOTSTRAP */
1:	rts
	  mov.b	r0, @r1

	.balign 4
led_addr:
	.long 0xa2100010
#ifdef SE_MODE_BOOTSTRAP
mmucr:  .long SH4_CCN_MMUCR
pmb_a:  .long SH4_PMB_ADDR_ARRAY_ENTRY(15)
pmb_d:  .long SH4_PMB_DATA_ARRAY_ENTRY(15)
v_a:    .long 0xbf000000
p_a:    .long 0x02000100
led2:   .long 0xbf100010
#endif /* SE_MODE_BOOTSTRAP */

/*
 * The poke table is a series of long words, in the format
 *
 *       opcode, address, operand, ...
 *
 * An opcode of 0 marks the table end
 */

#define POKE_UPDATE_LONG(A1, A2, AND, SHIFT, OR)	.long 8, A1, A2, AND, SHIFT, OR
#define WHILE_NE(A, AND, VAL)				.long 7, A, AND, VAL
#define UPDATE_LONG(A, AND, OR)				.long 6, A, AND, OR
#define OR_LONG(A, V)					.long 5, A, V
#define POKE_LONG(A, V)					.long 4, A, V
#define POKE_SHORT(A, V)				.long 2, A, V
#define POKE_CHAR(A, V)					.long 1, A, V
#define END_MARKER					.long 0, 0, 0

.balign 4

__memory_setup_table:

#ifdef PREPOKEINCLUDE
#include PREPOKEINCLUDE
#endif

	/*
	 * CLOCKGENA setup PLL0
	 */
	POKE_LONG(STB7109_CLOCKGENA_LOCK, 0xc0de)
	OR_LONG(STB7109_CLOCKGENA_PLL0_CFG, 0x00100000)
	UPDATE_LONG(STB7109_CLOCKGENA_PLL0_CFG, 0xfff7ffff, 0)
#ifdef TESTAPP_COCOREF
	UPDATE_LONG(STB7109_CLOCKGENA_PLL0_CFG, 0xfff80000, 0x14 | (0xb1 << 8) | (0x0 << 16))
#else
	UPDATE_LONG(STB7109_CLOCKGENA_PLL0_CFG, 0xfff80000, 0x06 | (0x3b << 8) | (0x0 << 16))
#endif
	OR_LONG(STB7109_CLOCKGENA_PLL0_CFG, 0x00080000)
	WHILE_NE(STB7109_CLOCKGENA_PLL0_STATUS, 0x00000001, 0x00000001)
	UPDATE_LONG(STB7109_CLOCKGENA_PLL0_CFG, 0xffefffff, 0)
	POKE_LONG(STB7109_CLOCKGENA_LOCK, 0x0)

	/*
	 * CLOCKGENA setup PLL1
	 */
	POKE_LONG(STB7109_CLOCKGENA_LOCK, 0xc0de)
	POKE_LONG(STB7109_CLOCKGENA_PLL1_BYPASS, 0x00000002)
	UPDATE_LONG(STB7109_CLOCKGENA_PLL1_CFG, 0xfff7ffff, 0)
#ifdef TESTAPP_COCOREF
	UPDATE_LONG(STB7109_CLOCKGENA_PLL1_CFG, 0xfff80000, 0x1e | (0xc8 << 8) | (0x0 << 16))
#else
	UPDATE_LONG(STB7109_CLOCKGENA_PLL1_CFG, 0xfff80000, 0x1b | (0xc8 << 8) | (0x0 << 16))
#endif
	OR_LONG(STB7109_CLOCKGENA_PLL1_CFG, 0x00080000)
	WHILE_NE(STB7109_CLOCKGENA_PLL1_STATUS, 0x00000001, 0x00000001)
	POKE_LONG(STB7109_CLOCKGENA_PLL1_BYPASS, 0x00000000)
	POKE_LONG(STB7109_CLOCKGENA_LOCK, 0x0)

	/*
	 * SYSCONF setup
	 */
#if STB7109_MOVE_LMI_REGS
        /*
         * Re-map LMI SYS and LMI VID to area 6 addresses as well...will be our
         * standard cut 3.0 configuration.
         */
	POKE_LONG(STB7109_SYSCONF_SYS_CFG11, 0xad7fd4ea)
#else
	POKE_LONG(STB7109_SYSCONF_SYS_CFG11, 0x0d7fd4ea)
#endif
	WHILE_NE(STB7109_SYSCONF_SYS_STA12, (1 << 9) | (1 << 19), (1 << 9) | (1 << 19))
	WHILE_NE(STB7109_SYSCONF_SYS_STA13, (1 << 9) | (1 << 19), (1 << 9) | (1 << 19))
	POKE_LONG(STB7109_SYSCONF_SYS_CFG12, 0x4000000f | (0xf << 12) | (0xf << 23))
	POKE_LONG(STB7109_SYSCONF_SYS_CFG13, 0x4000000f | (0xf << 12) | (0xf << 23))

	/*
	 * LMI SYS setup
	 */
	POKE_LONG(ST40_LMI_MIM_0(SYS), 0x861a025f)
	POKE_LONG(ST40_LMI_MIM_1(SYS), 0x01010022)
	POKE_LONG(ST40_LMI_STR_0(SYS), 0x35b06455)
	POKE_LONG(ST40_LMI_SDRA0_0(SYS), 0x08001900)
	POKE_LONG(ST40_LMI_SDRA1_0(SYS), 0x08001900)
	POKE_LONG(ST40_LMI_SCR_0(SYS), 0x00000001)
	POKE_LONG(ST40_LMI_SCR_0(SYS), 0x00000003)
	POKE_LONG(ST40_LMI_SCR_0(SYS), 0x00000001)
	POKE_LONG(ST40_LMI_SCR_0(SYS), 0x00000002)
	POKE_LONG(ST40_LMI_SDMR0(SYS), 0x00000402)
	POKE_LONG(ST40_LMI_SDMR0(SYS), 0x00000133)
	POKE_LONG(ST40_LMI_SCR_0(SYS), 0x00000002)
	POKE_LONG(ST40_LMI_SCR_0(SYS), 0x00000004)
	POKE_LONG(ST40_LMI_SCR_0(SYS), 0x00000004)
	POKE_LONG(ST40_LMI_SCR_0(SYS), 0x00000004)
	POKE_LONG(ST40_LMI_SDMR0(SYS), 0x00000033)
	POKE_LONG(ST40_LMI_SCR_0(SYS), 0x00000000)

	/*
	 * LMI VID setup
	 */
	POKE_LONG(ST40_LMI_MIM_0(VID), 0x861a025f)
	POKE_LONG(ST40_LMI_MIM_1(VID), 0x01010022)
	POKE_LONG(ST40_LMI_STR_0(VID), 0x35b06455)
	POKE_LONG(ST40_LMI_SDRA0_0(VID), 0x14001900)
	POKE_LONG(ST40_LMI_SDRA1_0(VID), 0x14001900)
	POKE_LONG(ST40_LMI_SCR_0(VID), 0x00000001)
	POKE_LONG(ST40_LMI_SCR_0(VID), 0x00000003)
	POKE_LONG(ST40_LMI_SCR_0(VID), 0x00000001)
	POKE_LONG(ST40_LMI_SCR_0(VID), 0x00000002)
	POKE_LONG(ST40_LMI_SDMR0(VID), 0x00000402)
	POKE_LONG(ST40_LMI_SDMR0(VID), 0x00000133)
	POKE_LONG(ST40_LMI_SCR_0(VID), 0x00000002)
	POKE_LONG(ST40_LMI_SCR_0(VID), 0x00000004)
	POKE_LONG(ST40_LMI_SCR_0(VID), 0x00000004)
	POKE_LONG(ST40_LMI_SCR_0(VID), 0x00000004)
	POKE_LONG(ST40_LMI_SDMR0(VID), 0x00000033)
	POKE_LONG(ST40_LMI_SCR_0(VID), 0x00000000)

	/*
	 * EMI setup
	 */