interlace.fit.eqn

一个简单的交织实现程序

--L1_ram[14] is jie_RAM_MN_dual2:inst10|ram[14] at LCFF_X27_Y30_N23
L1_ram[14] = DFFEAS(L1L58, GLOBAL(A1L3),  ,  ,  ,  ,  ,  ,  );


--L1L26 is jie_RAM_MN_dual2:inst10|Mux~64 at LCCOMB_X25_Y31_N10
L1L26 = K1_seq_addr[2] & (L1L25 & (L1_ram[14]) # !L1L25 & L1_ram[12]) # !K1_seq_addr[2] & L1L25;


--L1L27 is jie_RAM_MN_dual2:inst10|Mux~65 at LCCOMB_X25_Y31_N4
L1L27 = L1L24 & (L1L26 # !C1_series_addr[0]) # !L1L24 & L1L19 & C1_series_addr[0];


--D1_ram[8] is jie_RAM_MN_dual:inst2|ram[8] at LCFF_X27_Y30_N25
D1_ram[8] = DFFEAS(D1L30, GLOBAL(A1L3),  ,  ,  ,  ,  ,  ,  );


--D1_ram[11] is jie_RAM_MN_dual:inst2|ram[11] at LCFF_X24_Y31_N1
D1_ram[11] = DFFEAS(D1L36, GLOBAL(A1L3),  ,  ,  ,  ,  ,  ,  );


--D1_ram[9] is jie_RAM_MN_dual:inst2|ram[9] at LCFF_X24_Y31_N11
D1_ram[9] = DFFEAS(D1L32, GLOBAL(A1L3),  ,  ,  ,  ,  ,  ,  );


--D1L2 is jie_RAM_MN_dual:inst2|Mux~56 at LCCOMB_X25_Y30_N26
D1L2 = C1_series_addr[0] & (K1_seq_addr[1]) # !C1_series_addr[0] & (K1_seq_addr[1] & D1_ram[11] # !K1_seq_addr[1] & (D1_ram[9]));


--D1_ram[10] is jie_RAM_MN_dual:inst2|ram[10] at LCFF_X27_Y30_N5
D1_ram[10] = DFFEAS(D1L34, GLOBAL(A1L3),  ,  ,  ,  ,  ,  ,  );


--D1L3 is jie_RAM_MN_dual:inst2|Mux~57 at LCCOMB_X25_Y30_N10
D1L3 = D1L2 & (D1_ram[10] # !C1_series_addr[0]) # !D1L2 & D1_ram[8] & C1_series_addr[0];


--D1_ram[4] is jie_RAM_MN_dual:inst2|ram[4] at LCFF_X24_Y31_N9
D1_ram[4] = DFFEAS(D1L22, GLOBAL(A1L3),  ,  ,  ,  ,  ,  ,  );


--D1_ram[7] is jie_RAM_MN_dual:inst2|ram[7] at LCFF_X27_Y30_N21
D1_ram[7] = DFFEAS(D1L28, GLOBAL(A1L3),  ,  ,  ,  ,  ,  ,  );


--D1_ram[5] is jie_RAM_MN_dual:inst2|ram[5] at LCFF_X27_Y30_N15
D1_ram[5] = DFFEAS(D1L24, GLOBAL(A1L3),  ,  ,  ,  ,  ,  ,  );


--D1L4 is jie_RAM_MN_dual:inst2|Mux~58 at LCCOMB_X25_Y30_N2
D1L4 = C1_series_addr[0] & (K1_seq_addr[1]) # !C1_series_addr[0] & (K1_seq_addr[1] & D1_ram[7] # !K1_seq_addr[1] & (D1_ram[5]));


--D1_ram[6] is jie_RAM_MN_dual:inst2|ram[6] at LCFF_X24_Y31_N5
D1_ram[6] = DFFEAS(D1L26, GLOBAL(A1L3),  ,  ,  ,  ,  ,  ,  );


--D1L5 is jie_RAM_MN_dual:inst2|Mux~59 at LCCOMB_X25_Y30_N16
D1L5 = D1L4 & (D1_ram[6] # !C1_series_addr[0]) # !D1L4 & D1_ram[4] & C1_series_addr[0];


--D1_ram[0] is jie_RAM_MN_dual:inst2|ram[0] at LCFF_X27_Y31_N21
D1_ram[0] = DFFEAS(D1L14, GLOBAL(A1L3),  ,  ,  ,  ,  ,  ,  );


--D1_ram[3] is jie_RAM_MN_dual:inst2|ram[3] at LCFF_X27_Y30_N31
D1_ram[3] = DFFEAS(D1L20, GLOBAL(A1L3),  ,  ,  ,  ,  ,  ,  );


--D1_ram[1] is jie_RAM_MN_dual:inst2|ram[1] at LCFF_X24_Y31_N23
D1_ram[1] = DFFEAS(D1L16, GLOBAL(A1L3),  ,  ,  ,  ,  ,  ,  );


--D1L6 is jie_RAM_MN_dual:inst2|Mux~60 at LCCOMB_X25_Y30_N4
D1L6 = C1_series_addr[0] & (K1_seq_addr[1]) # !C1_series_addr[0] & (K1_seq_addr[1] & D1_ram[3] # !K1_seq_addr[1] & (D1_ram[1]));


--D1_ram[2] is jie_RAM_MN_dual:inst2|ram[2] at LCFF_X24_Y31_N17
D1_ram[2] = DFFEAS(D1L18, GLOBAL(A1L3),  ,  ,  ,  ,  ,  ,  );


--D1L7 is jie_RAM_MN_dual:inst2|Mux~61 at LCCOMB_X25_Y30_N28
D1L7 = C1_series_addr[0] & (D1L6 & (D1_ram[2]) # !D1L6 & D1_ram[0]) # !C1_series_addr[0] & D1L6;


--D1L8 is jie_RAM_MN_dual:inst2|Mux~62 at LCCOMB_X25_Y30_N22
D1L8 = K1_seq_addr[3] & (K1_seq_addr[2]) # !K1_seq_addr[3] & (K1_seq_addr[2] & D1L5 # !K1_seq_addr[2] & (D1L7));


--D1_ram[12] is jie_RAM_MN_dual:inst2|ram[12] at LCFF_X27_Y30_N27
D1_ram[12] = DFFEAS(D1L38, GLOBAL(A1L3),  ,  ,  ,  ,  ,  ,  );


--D1_ram[15] is jie_RAM_MN_dual:inst2|ram[15] at LCFF_X24_Y31_N25
D1_ram[15] = DFFEAS(D1L44, GLOBAL(A1L3),  ,  ,  ,  ,  ,  ,  );


--D1_ram[13] is jie_RAM_MN_dual:inst2|ram[13] at LCFF_X24_Y31_N21
D1_ram[13] = DFFEAS(D1L40, GLOBAL(A1L3),  ,  ,  ,  ,  ,  ,  );


--D1L9 is jie_RAM_MN_dual:inst2|Mux~63 at LCCOMB_X25_Y30_N12
D1L9 = C1_series_addr[0] & (K1_seq_addr[1]) # !C1_series_addr[0] & (K1_seq_addr[1] & D1_ram[15] # !K1_seq_addr[1] & (D1_ram[13]));


--D1_ram[14] is jie_RAM_MN_dual:inst2|ram[14] at LCFF_X27_Y30_N17
D1_ram[14] = DFFEAS(D1L42, GLOBAL(A1L3),  ,  ,  ,  ,  ,  ,  );


--D1L10 is jie_RAM_MN_dual:inst2|Mux~64 at LCCOMB_X25_Y30_N6
D1L10 = D1L9 & (D1_ram[14] # !C1_series_addr[0]) # !D1L9 & D1_ram[12] & C1_series_addr[0];


--D1L11 is jie_RAM_MN_dual:inst2|Mux~65 at LCCOMB_X25_Y30_N8
D1L11 = D1L8 & (D1L10 # !K1_seq_addr[3]) # !D1L8 & D1L3 & K1_seq_addr[3];


--C1_cnt[4] is jie_counter:inst1|cnt[4] at LCFF_X28_Y32_N21
C1_cnt[4] = DFFEAS(C1L7, GLOBAL(A1L3),  ,  ,  ,  ,  ,  ,  );


--C1_cnt[8] is jie_counter:inst1|cnt[8] at LCFF_X28_Y32_N29
C1_cnt[8] = DFFEAS(C1L15, GLOBAL(A1L3),  ,  ,  ,  ,  ,  ,  );


--C1_cnt[7] is jie_counter:inst1|cnt[7] at LCFF_X28_Y32_N27
C1_cnt[7] = DFFEAS(C1L13, GLOBAL(A1L3),  ,  ,  ,  ,  ,  ,  );


--C1_cnt[6] is jie_counter:inst1|cnt[6] at LCFF_X28_Y32_N25
C1_cnt[6] = DFFEAS(C1L11, GLOBAL(A1L3),  ,  ,  ,  ,  ,  ,  );


--C1_cnt[5] is jie_counter:inst1|cnt[5] at LCFF_X28_Y32_N11
C1_cnt[5] = DFFEAS(C1L23, GLOBAL(A1L3),  ,  ,  ,  ,  ,  ,  );


--A1L22 is rtl~53 at LCCOMB_X28_Y32_N6
A1L22 = !C1_cnt[5] & !C1_cnt[8] & !C1_cnt[6] & !C1_cnt[7];


--J1L1 is counter:inst8|ch~36 at LCCOMB_X28_Y32_N8
J1L1 = !C1_cnt[4] & A1L22;


--C1L31 is jie_counter:inst1|series_addr[3]~60 at LCCOMB_X28_Y32_N2
C1L31 = C1_series_addr[3] $ (C1_series_addr[0] & C1_series_addr[1] & C1_series_addr[2]);


--C1L29 is jie_counter:inst1|series_addr[2]~61 at LCCOMB_X28_Y32_N4
C1L29 = C1_series_addr[2] $ (C1_series_addr[1] & C1_series_addr[0]);


--C1L1 is jie_counter:inst1|add~216 at LCCOMB_X28_Y32_N14
C1L1 = C1_series_addr[0] & (C1_series_addr[1] $ VCC) # !C1_series_addr[0] & C1_series_addr[1] & VCC;

--C1L2 is jie_counter:inst1|add~217 at LCCOMB_X28_Y32_N14
C1L2 = CARRY(C1_series_addr[0] & C1_series_addr[1]);


--G1L1 is RAM_MN_dual:inst5|Decoder~241 at LCCOMB_X28_Y31_N20
G1L1 = C1_series_addr[0] & K1_seq_addr[3] & K1_seq_addr[1] & K1_seq_addr[2];


--G1L58 is RAM_MN_dual:inst5|ram[14]~961 at LCCOMB_X28_Y32_N0
G1L58 = G1L1 & (inst14 & (datain) # !inst14 & G1_ram[14]) # !G1L1 & (G1_ram[14]);


--G1L2 is RAM_MN_dual:inst5|Decoder~242 at LCCOMB_X28_Y31_N2
G1L2 = !C1_series_addr[0] & K1_seq_addr[3] & !K1_seq_addr[1] & K1_seq_addr[2];


--G1L56 is RAM_MN_dual:inst5|ram[13]~962 at LCCOMB_X29_Y31_N10
G1L56 = G1L2 & (inst14 & (datain) # !inst14 & G1_ram[13]) # !G1L2 & (G1_ram[13]);


--G1L3 is RAM_MN_dual:inst5|Decoder~243 at LCCOMB_X28_Y31_N10
G1L3 = C1_series_addr[0] & K1_seq_addr[3] & !K1_seq_addr[1] & K1_seq_addr[2];


--G1L54 is RAM_MN_dual:inst5|ram[12]~963 at LCCOMB_X29_Y31_N24
G1L54 = G1L3 & (inst14 & (datain) # !inst14 & G1_ram[12]) # !G1L3 & (G1_ram[12]);


--G1L4 is RAM_MN_dual:inst5|Decoder~244 at LCCOMB_X28_Y31_N12
G1L4 = !C1_series_addr[0] & K1_seq_addr[3] & K1_seq_addr[1] & K1_seq_addr[2];


--G1L60 is RAM_MN_dual:inst5|ram[15]~964 at LCCOMB_X29_Y31_N28
G1L60 = G1L4 & (inst14 & (datain) # !inst14 & G1_ram[15]) # !G1L4 & (G1_ram[15]);


--G1L5 is RAM_MN_dual:inst5|Decoder~245 at LCCOMB_X28_Y31_N14
G1L5 = !C1_series_addr[0] & !K1_seq_addr[3] & !K1_seq_addr[1] & !K1_seq_addr[2];


--G1L32 is RAM_MN_dual:inst5|ram[1]~965 at LCCOMB_X29_Y31_N14
G1L32 = G1L5 & (inst14 & (datain) # !inst14 & G1_ram[1]) # !G1L5 & (G1_ram[1]);


--G1L6 is RAM_MN_dual:inst5|Decoder~246 at LCCOMB_X28_Y30_N16
G1L6 = !K1_seq_addr[2] & C1_series_addr[0] & !K1_seq_addr[3] & K1_seq_addr[1];


--G1L34 is RAM_MN_dual:inst5|ram[2]~966 at LCCOMB_X29_Y31_N8
G1L34 = inst14 & (G1L6 & (datain) # !G1L6 & G1_ram[2]) # !inst14 & (G1_ram[2]);


--G1L7 is RAM_MN_dual:inst5|Decoder~247 at LCCOMB_X25_Y31_N18
G1L7 = !K1_seq_addr[3] & !K1_seq_addr[1] & C1_series_addr[0] & !K1_seq_addr[2];


--G1L30 is RAM_MN_dual:inst5|ram[0]~967 at LCCOMB_X29_Y31_N18
G1L30 = G1L7 & (inst14 & (datain) # !inst14 & G1_ram[0]) # !G1L7 & (G1_ram[0]);


--G1L8 is RAM_MN_dual:inst5|Decoder~248 at LCCOMB_X28_Y30_N6
G1L8 = !K1_seq_addr[2] & !C1_series_addr[0] & !K1_seq_addr[3] & K1_seq_addr[1];


--G1L36 is RAM_MN_dual:inst5|ram[3]~968 at LCCOMB_X29_Y31_N30
G1L36 = G1L8 & (inst14 & (datain) # !inst14 & G1_ram[3]) # !G1L8 & (G1_ram[3]);


--G1L9 is RAM_MN_dual:inst5|Decoder~249 at LCCOMB_X25_Y31_N22
G1L9 = K1_seq_addr[3] & K1_seq_addr[1] & C1_series_addr[0] & !K1_seq_addr[2];


--G1L50 is RAM_MN_dual:inst5|ram[10]~969 at LCCOMB_X29_Y31_N2
G1L50 = G1L9 & (inst14 & (datain) # !inst14 & G1_ram[10]) # !G1L9 & (G1_ram[10]);


--G1L10 is RAM_MN_dual:inst5|Decoder~250 at LCCOMB_X27_Y31_N24
G1L10 = !K1_seq_addr[2] & K1_seq_addr[3] & !C1_series_addr[0] & !K1_seq_addr[1];


--G1L48 is RAM_MN_dual:inst5|ram[9]~970 at LCCOMB_X27_Y31_N4
G1L48 = G1L10 & (inst14 & (datain) # !inst14 & G1_ram[9]) # !G1L10 & (G1_ram[9]);


--G1L11 is RAM_MN_dual:inst5|Decoder~251 at LCCOMB_X27_Y31_N10
G1L11 = !K1_seq_addr[2] & K1_seq_addr[3] & C1_series_addr[0] & !K1_seq_addr[1];


--G1L46 is RAM_MN_dual:inst5|ram[8]~971 at LCCOMB_X27_Y31_N2
G1L46 = G1L11 & (inst14 & (datain) # !inst14 & G1_ram[8]) # !G1L11 & (G1_ram[8]);


--G1L12 is RAM_MN_dual:inst5|Decoder~252 at LCCOMB_X27_Y31_N6
G1L12 = !K1_seq_addr[2] & K1_seq_addr[3] & !C1_series_addr[0] & K1_seq_addr[1];


--G1L52 is RAM_MN_dual:inst5|ram[11]~972 at LCCOMB_X27_Y30_N10
G1L52 = G1L12 & (inst14 & (datain) # !inst14 & G1_ram[11]) # !G1L12 & (G1_ram[11]);


--G1L13 is RAM_MN_dual:inst5|Decoder~253 at LCCOMB_X27_Y31_N22
G1L13 = K1_seq_addr[2] & !K1_seq_addr[3] & !C1_series_addr[0] & !K1_seq_addr[1];


--G1L40 is RAM_MN_dual:inst5|ram[5]~973 at LCCOMB_X29_Y30_N8
G1L40 = G1L13 & (inst14 & (datain) # !inst14 & G1_ram[5]) # !G1L13 & (G1_ram[5]);


--G1L14 is RAM_MN_dual:inst5|Decoder~254 at LCCOMB_X28_Y30_N14
G1L14 = K1_seq_addr[2] & C1_series_addr[0] & !K1_seq_addr[3] & K1_seq_addr[1];


--G1L42 is RAM_MN_dual:inst5|ram[6]~974 at LCCOMB_X29_Y30_N20
G1L42 = G1L14 & (inst14 & (datain) # !inst14 & G1_ram[6]) # !G1L14 & (G1_ram[6]);


--G1L15 is RAM_MN_dual:inst5|Decoder~255 at LCCOMB_X25_Y30_N24
G1L15 = C1_series_addr[0] & !K1_seq_addr[3] & !K1_seq_addr[1] & K1_seq_addr[2];


--G1L38 is RAM_MN_dual:inst5|ram[4]~975 at LCCOMB_X29_Y30_N4
G1L38 = G1L15 & (inst14 & (datain) # !inst14 & G1_ram[4]) # !G1L15 & (G1_ram[4]);


--G1L16 is RAM_MN_dual:inst5|Decoder~256 at LCCOMB_X25_Y31_N2
G1L16 = !K1_seq_addr[3] & K1_seq_addr[1] & !C1_series_addr[0] & K1_seq_addr[2];


--G1L44 is RAM_MN_dual:inst5|ram[7]~976 at LCCOMB_X29_Y30_N0
G1L44 = G1L16 & (inst14 & (datain) # !inst14 & G1_ram[7]) # !G1L16 & (G1_ram[7]);


--H1L22 is RAM_MN_dual2:inst6|ram[4]~961 at LCCOMB_X29_Y30_N10
H1L22 = G1L15 & (inst14 & H1_ram[4] # !inst14 & (datain)) # !G1L15 & (H1_ram[4]);


--H1L42 is RAM_MN_dual2:inst6|ram[14]~962 at LCCOMB_X28_Y32_N12
H1L42 = G1L1 & (inst14 & H1_ram[14] # !inst14 & (datain)) # !G1L1 & (H1_ram[14]);


--H1L38 is RAM_MN_dual2:inst6|ram[12]~963 at LCCOMB_X29_Y31_N6
H1L38 = G1L3 & (inst14 & H1_ram[12] # !inst14 & (datain)) # !G1L3 & (H1_ram[12]);


--H1L26 is RAM_MN_dual2:inst6|ram[6]~964 at LCCOMB_X29_Y30_N28
H1L26 = G1L14 & (inst14 & H1_ram[6] # !inst14 & (datain)) # !G1L14 & (H1_ram[6]);


--H1L16 is RAM_MN_dual2:inst6|ram[1]~965 at LCCOMB_X29_Y31_N0
H1L16 = G1L5 & (inst14 & H1_ram[1] # !inst14 & (datain)) # !G1L5 & (H1_ram[1]);


--H1L36 is RAM_MN_dual2:inst6|ram[11]~966 at LCCOMB_X27_Y30_N18
H1L36 = G1L12 & (inst14 & H1_ram[11] # !inst14 & (datain)) # !G1L12 & (H1_ram[11]);


--H1L32 is RAM_MN_dual2:inst6|ram[9]~967 at LCCOMB_X27_Y31_N26
H1L32 = G1L10 & (inst14 & H1_ram[9] # !inst14 & (datain)) # !G1L10 & (H1_ram[9]);


--H1L20 is RAM_MN_dual2:inst6|ram[3]~968 at LCCOMB_X29_Y31_N16
H1L20 = G1L8 & (inst14 & H1_ram[3] # !inst14 & (datain)) # !G1L8 & (H1_ram[3]);


--H1L14 is RAM_MN_dual2:inst6|ram[0]~969 at LCCOMB_X29_Y31_N4
H1L14 = G1L7 & (inst14 & H1_ram[0] # !inst14 & (datain)) # !G1L7 & (H1_ram[0]);


--H1L34 is RAM_MN_dual2:inst6|ram[10]~970 at LCCOMB_X29_Y31_N26
H1L34 = G1L9 & (inst14 & H1_ram[10] # !inst14 & (datain)) # !G1L9 & (H1_ram[10]);


--H1L30 is RAM_MN_dual2:inst6|ram[8]~971 at LCCOMB_X27_Y31_N12
H1L30 = G1L11 & (inst14 & H1_ram[8] # !inst14 & (datain)) # !G1L11 & (H1_ram[8]);


--H1L18 is RAM_MN_dual2:inst6|ram[2]~972 at LCCOMB_X29_Y31_N20
H1L18 = inst14 & (H1_ram[2]) # !inst14 & (G1L6 & (datain) # !G1L6 & H1_ram[2]);


--H1L44 is RAM_MN_dual2:inst6|ram[15]~973 at LCCOMB_X29_Y31_N22
H1L44 = G1L4 & (inst14 & H1_ram[15] # !inst14 & (datain)) # !G1L4 & (H1_ram[15]);


--H1L24 is RAM_MN_dual2:inst6|ram[5]~974 at LCCOMB_X29_Y30_N12
H1L24 = G1L13 & (inst14 & H1_ram[5] # !inst14 & (datain)) # !G1L13 & (H1_ram[5]);


--H1L40 is RAM_MN_dual2:inst6|ram[13]~975 at LCCOMB_X29_Y31_N12
H1L40 = G1L2 & (inst14 & H1_ram[13] # !inst14 & (datain)) # !G1L2 & (H1_ram[13]);


--H1L28 is RAM_MN_dual2:inst6|ram[7]~976 at LCCOMB_X29_Y30_N30
H1L28 = G1L16 & (inst14 & H1_ram[7] # !inst14 & (datain)) # !G1L16 & (H1_ram[7]);


--L1L1 is jie_RAM_MN_dual2:inst10|Decoder~321 at LCCOMB_X25_Y30_N14
L1L1 = C1_series_addr[0] & !K1_seq_addr[3] & K1_seq_addr[1] & !K1_seq_addr[2];


--L1L38 is jie_RAM_MN_dual2:inst10|ram[4]~1601 at LCCOMB_X24_Y31_N18
L1L38 = inst14 & (L1L1 & (E1L1) # !L1L1 & L1_ram[4]) # !inst14 & (L1_ram[4]);


--L1L2 is jie_RAM_MN_dual2:inst10|Decoder~322 at LCCOMB_X25_Y30_N30
L1L2 = !C1_series_addr[0] & K1_seq_addr[3] & K1_seq_addr[1] & !K1_seq_addr[2];


--L1L34 is jie_RAM_MN_dual2:inst10|ram[2]~1602 at LCCOMB_X24_Y31_N30
L1L34 = inst14 & (L1L2 & E1L1 # !L1L2 & (L1_ram[2])) # !inst14 & (L1_ram[2]);