jiaozhijiejiaozhi.map.qmsg

来自「一个简单的交织实现程序」· QMSG 代码 · 共 53 行 · 第 1/3 页

{ "Warning" "WGDFX_INCONSISTENT_BASE_NAME" "" "Warning: Found multiple base names" {  } { { "interlace.bdf" "" { Schematic "F:/liangshuo程序/1/fen_zu_interlacing/interlace.bdf" { { -528 456 632 -512 "cnt2\[4..0\]" "" } { -528 456 632 -512 "cnt2\[4..0\]" "" } { -528 456 632 -512 "cnt2\[4..0\]" "" } { -528 456 632 -512 "cnt2\[4..0\]" "" } { -528 456 632 -512 "cnt2\[4..0\]" "" } { -528 456 632 -512 "cnt2\[4..0\]" "" } } } }  } 0 0 "Found multiple base names" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter1 interlace:inst\|counter1:inst5 " "Info: Elaborating entity \"counter1\" for hierarchy \"interlace:inst\|counter1:inst5\"" {  } { { "interlace.bdf" "inst5" { Schematic "F:/liangshuo程序/1/fen_zu_interlacing/interlace.bdf" { { -384 -104 48 -288 "inst5" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "source.vhd 2 1 " "Warning: Using design file source.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 source-a " "Info: Found design unit 1: source-a" {  } { { "source.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/source.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 source " "Info: Found entity 1: source" {  } { { "source.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/source.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "source interlace:inst\|source:inst1 " "Info: Elaborating entity \"source\" for hierarchy \"interlace:inst\|source:inst1\"" {  } { { "interlace.bdf" "inst1" { Schematic "F:/liangshuo程序/1/fen_zu_interlacing/interlace.bdf" { { -144 144 240 -48 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WOPT_RAM_FUNCTIONALITY_CHANGE_ALTSYNCRAM_DUAL_CLOCK" "jieinterlace:inst1\|RAM_MN_dual2:inst6\|ram\[0\]~60 " "Warning: Created node \"jieinterlace:inst1\|RAM_MN_dual2:inst6\|ram\[0\]~60\" as a dual-clock RAM by generating altsyncram megafunction to implement register logic with M512 or M4K memory block or M-RAM. Functionality differs from the original design." {  } { { "RAM_MN_dual2.vhd" "ram\[0\]~60" { Text "F:/liangshuo程序/1/fen_zu_interlacing/RAM_MN_dual2.vhd" 27 -1 0 } }  } 0 0 "Created node \"%1!s!\" as a dual-clock RAM by generating altsyncram megafunction to implement register logic with M512 or M4K memory block or M-RAM. Functionality differs from the original design." 0 0}
{ "Warning" "WOPT_RAM_FUNCTIONALITY_CHANGE_ALTSYNCRAM_DUAL_CLOCK" "jieinterlace:inst1\|RAM_MN_dual:inst5\|ram\[0\]~60 " "Warning: Created node \"jieinterlace:inst1\|RAM_MN_dual:inst5\|ram\[0\]~60\" as a dual-clock RAM by generating altsyncram megafunction to implement register logic with M512 or M4K memory block or M-RAM. Functionality differs from the original design." {  } { { "RAM_MN_dual.vhd" "ram\[0\]~60" { Text "F:/liangshuo程序/1/fen_zu_interlacing/RAM_MN_dual.vhd" 29 -1 0 } }  } 0 0 "Created node \"%1!s!\" as a dual-clock RAM by generating altsyncram megafunction to implement register logic with M512 or M4K memory block or M-RAM. Functionality differs from the original design." 0 0}
{ "Warning" "WOPT_RAM_FUNCTIONALITY_CHANGE_ALTSYNCRAM_DUAL_CLOCK" "interlace:inst\|RAM_MN_dual2:inst6\|ram\[0\]~60 " "Warning: Created node \"interlace:inst\|RAM_MN_dual2:inst6\|ram\[0\]~60\" as a dual-clock RAM by generating altsyncram megafunction to implement register logic with M512 or M4K memory block or M-RAM. Functionality differs from the original design." {  } { { "RAM_MN_dual2.vhd" "ram\[0\]~60" { Text "F:/liangshuo程序/1/fen_zu_interlacing/RAM_MN_dual2.vhd" 27 -1 0 } }  } 0 0 "Created node \"%1!s!\" as a dual-clock RAM by generating altsyncram megafunction to implement register logic with M512 or M4K memory block or M-RAM. Functionality differs from the original design." 0 0}
{ "Warning" "WOPT_RAM_FUNCTIONALITY_CHANGE_ALTSYNCRAM_DUAL_CLOCK" "interlace:inst\|RAM_MN_dual:inst2\|ram\[0\]~60 " "Warning: Created node \"interlace:inst\|RAM_MN_dual:inst2\|ram\[0\]~60\" as a dual-clock RAM by generating altsyncram megafunction to implement register logic with M512 or M4K memory block or M-RAM. Functionality differs from the original design." {  } { { "RAM_MN_dual.vhd" "ram\[0\]~60" { Text "F:/liangshuo程序/1/fen_zu_interlacing/RAM_MN_dual.vhd" 29 -1 0 } }  } 0 0 "Created node \"%1!s!\" as a dual-clock RAM by generating altsyncram megafunction to implement register logic with M512 or M4K memory block or M-RAM. Functionality differs from the original design." 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "interlace:inst\|counter1:inst5\|cnt\[5\] jieinterlace:inst1\|counter2:inst1\|cnt\[5\] " "Info: Duplicate register \"interlace:inst\|counter1:inst5\|cnt\[5\]\" merged to single register \"jieinterlace:inst1\|counter2:inst1\|cnt\[5\]\"" {  } { { "counter1.v" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/counter1.v" 17 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "interlace:inst\|counter1:inst5\|cnt\[4\] jieinterlace:inst1\|counter2:inst1\|cnt\[4\] " "Info: Duplicate register \"interlace:inst\|counter1:inst5\|cnt\[4\]\" merged to single register \"jieinterlace:inst1\|counter2:inst1\|cnt\[4\]\"" {  } { { "counter1.v" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/counter1.v" 17 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "interlace:inst\|counter1:inst5\|cnt\[3\] jieinterlace:inst1\|counter2:inst1\|cnt\[3\] " "Info: Duplicate register \"interlace:inst\|counter1:inst5\|cnt\[3\]\" merged to single register \"jieinterlace:inst1\|counter2:inst1\|cnt\[3\]\"" {  } { { "counter1.v" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/counter1.v" 17 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "interlace:inst\|counter1:inst5\|cnt\[2\] jieinterlace:inst1\|counter2:inst1\|cnt\[2\] " "Info: Duplicate register \"interlace:inst\|counter1:inst5\|cnt\[2\]\" merged to single register \"jieinterlace:inst1\|counter2:inst1\|cnt\[2\]\"" {  } { { "counter1.v" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/counter1.v" 17 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "interlace:inst\|counter1:inst5\|cnt\[1\] jieinterlace:inst1\|counter2:inst1\|cnt\[1\] " "Info: Duplicate register \"interlace:inst\|counter1:inst5\|cnt\[1\]\" merged to single register \"jieinterlace:inst1\|counter2:inst1\|cnt\[1\]\"" {  } { { "counter1.v" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/counter1.v" 17 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "interlace:inst\|counter1:inst5\|series_addr\[0\] interlace:inst\|rom_mn_seq:inst9\|seq_addr\[0\] " "Info: Duplicate register \"interlace:inst\|counter1:inst5\|series_addr\[0\]\" merged to single register \"interlace:inst\|rom_mn_seq:inst9\|seq_addr\[0\]\", power-up level changed" {  } { { "counter1.v" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/counter1.v" 11 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\", power-up level changed" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "interlace:inst\|source:inst1\|m\[0\] interlace:inst\|rom_mn_seq:inst9\|seq_addr\[0\] " "Info: Duplicate register \"interlace:inst\|source:inst1\|m\[0\]\" merged to single register \"interlace:inst\|rom_mn_seq:inst9\|seq_addr\[0\]\", power-up level changed" {  } { { "source.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/source.vhd" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\", power-up level changed" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "jieinterlace:inst1\|counter2:inst1\|cnt\[0\] interlace:inst\|rom_mn_seq:inst9\|seq_addr\[0\] " "Info: Duplicate register \"jieinterlace:inst1\|counter2:inst1\|cnt\[0\]\" merged to single register \"interlace:inst\|rom_mn_seq:inst9\|seq_addr\[0\]\"" {  } { { "counter2.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/counter2.vhd" 31 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "interlace:inst\|source:inst1\|m\[1\] jieinterlace:inst1\|counter2:inst1\|cnt\[1\] " "Info: Duplicate register \"interlace:inst\|source:inst1\|m\[1\]\" merged to single register \"jieinterlace:inst1\|counter2:inst1\|cnt\[1\]\"" {  } { { "source.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/source.vhd" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "4 " "Info: Inferred 4 megafunctions from design logic" { { "Info" "IOPT_ALTSYNCRAM_INFERRED" "jieinterlace:inst1\|RAM_MN_dual2:inst6\|ram\[0\]~60 32 1 " "Info: Inferred altsyncram megafunction (NUMWORDS_A=32, WIDTH_A=1) from the following design logic: \"jieinterlace:inst1\|RAM_MN_dual2:inst6\|ram\[0\]~60\"" {  } { { "RAM_MN_dual2.vhd" "ram\[0\]~60" { Text "F:/liangshuo程序/1/fen_zu_interlacing/RAM_MN_dual2.vhd" 27 -1 0 } }  } 0 0 "Inferred altsyncram megafunction (NUMWORDS_A=%2!d!, WIDTH_A=%3!d!) from the following design logic: \"%1!s!\"" 0 0} { "Info" "IOPT_ALTSYNCRAM_INFERRED" "jieinterlace:inst1\|RAM_MN_dual:inst5\|ram\[0\]~60 32 1 " "Info: Inferred altsyncram megafunction (NUMWORDS_A=32, WIDTH_A=1) from the following design logic: \"jieinterlace:inst1\|RAM_MN_dual:inst5\|ram\[0\]~60\"" {  } { { "RAM_MN_dual.vhd" "ram\[0\]~60" { Text "F:/liangshuo程序/1/fen_zu_interlacing/RAM_MN_dual.vhd" 29 -1 0 } }  } 0 0 "Inferred altsyncram megafunction (NUMWORDS_A=%2!d!, WIDTH_A=%3!d!) from the following design logic: \"%1!s!\"" 0 0} { "Info" "IOPT_ALTSYNCRAM_INFERRED" "interlace:inst\|RAM_MN_dual2:inst6\|ram\[0\]~60 32 1 " "Info: Inferred altsyncram megafunction (NUMWORDS_A=32, WIDTH_A=1) from the following design logic: \"interlace:inst\|RAM_MN_dual2:inst6\|ram\[0\]~60\"" {  } { { "RAM_MN_dual2.vhd" "ram\[0\]~60" { Text "F:/liangshuo程序/1/fen_zu_interlacing/RAM_MN_dual2.vhd" 27 -1 0 } }  } 0 0 "Inferred altsyncram megafunction (NUMWORDS_A=%2!d!, WIDTH_A=%3!d!) from the following design logic: \"%1!s!\"" 0 0} { "Info" "IOPT_ALTSYNCRAM_INFERRED" "interlace:inst\|RAM_MN_dual:inst2\|ram\[0\]~60 32 1 " "Info: Inferred altsyncram megafunction (NUMWORDS_A=32, WIDTH_A=1) from the following design logic: \"interlace:inst\|RAM_MN_dual:inst2\|ram\[0\]~60\"" {  } { { "RAM_MN_dual.vhd" "ram\[0\]~60" { Text "F:/liangshuo程序/1/fen_zu_interlacing/RAM_MN_dual.vhd" 29 -1 0 } }  } 0 0 "Inferred altsyncram megafunction (NUMWORDS_A=%2!d!, WIDTH_A=%3!d!) from the following design logic: \"%1!s!\"" 0 0}  } {  } 0 0 "Inferred %1!d! megafunctions from design logic" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/program files/altera/quartus60/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus60/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "d:/program files/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 426 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "jieinterlace:inst1\|RAM_MN_dual2:inst6\|altsyncram:ram_rtl_0 " "Info: Elaborated megafunction instantiation \"jieinterlace:inst1\|RAM_MN_dual2:inst6\|altsyncram:ram_rtl_0\"" {  } {  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_1qe1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_1qe1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_1qe1 " "Info: Found entity 1: altsyncram_1qe1" {  } { { "db/altsyncram_1qe1.tdf" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/db/altsyncram_1qe1.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "72 " "Info: Implemented 72 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "15 " "Info: Implemented 15 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "52 " "Info: Implemented 52 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0} { "Info" "ISCL_SCL_TM_RAMS" "4 " "Info: Implemented 4 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 21 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 21 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 09 12:10:33 2008 " "Info: Processing ended: Wed Apr 09 12:10:33 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}