interlace.tan.qmsg

来自「一个简单的交织实现程序」· QMSG 代码 · 共 8 行 · 第 1/2 页

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk memory RAM_MN_dual2:inst6\|altsyncram:ram_rtl_1\|altsyncram_rmi1:auto_generated\|ram_block1a0~portb_address_reg0 register RAM_MN_dual2:inst6\|dout 370.92 MHz 2.696 ns Internal " "Info: Clock \"clk\" has Internal fmax of 370.92 MHz between source memory \"RAM_MN_dual2:inst6\|altsyncram:ram_rtl_1\|altsyncram_rmi1:auto_generated\|ram_block1a0~portb_address_reg0\" and destination register \"RAM_MN_dual2:inst6\|dout\" (period= 2.696 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.639 ns + Longest memory register " "Info: + Longest memory to register delay is 2.639 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns RAM_MN_dual2:inst6\|altsyncram:ram_rtl_1\|altsyncram_rmi1:auto_generated\|ram_block1a0~portb_address_reg0 1 MEM M4K_X31_Y31 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X31_Y31; Fanout = 1; MEM Node = 'RAM_MN_dual2:inst6\|altsyncram:ram_rtl_1\|altsyncram_rmi1:auto_generated\|ram_block1a0~portb_address_reg0'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { RAM_MN_dual2:inst6|altsyncram:ram_rtl_1|altsyncram_rmi1:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } } { "db/altsyncram_rmi1.tdf" "" { Text "F:/111/fen_zu_interlacing/db/altsyncram_rmi1.tdf" 46 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.850 ns) 1.850 ns RAM_MN_dual2:inst6\|altsyncram:ram_rtl_1\|altsyncram_rmi1:auto_generated\|q_b\[0\] 2 MEM M4K_X31_Y31 1 " "Info: 2: + IC(0.000 ns) + CELL(1.850 ns) = 1.850 ns; Loc. = M4K_X31_Y31; Fanout = 1; MEM Node = 'RAM_MN_dual2:inst6\|altsyncram:ram_rtl_1\|altsyncram_rmi1:auto_generated\|q_b\[0\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.850 ns" { RAM_MN_dual2:inst6|altsyncram:ram_rtl_1|altsyncram_rmi1:auto_generated|ram_block1a0~portb_address_reg0 RAM_MN_dual2:inst6|altsyncram:ram_rtl_1|altsyncram_rmi1:auto_generated|q_b[0] } "NODE_NAME" } } { "db/altsyncram_rmi1.tdf" "" { Text "F:/111/fen_zu_interlacing/db/altsyncram_rmi1.tdf" 42 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.581 ns) + CELL(0.053 ns) 2.484 ns RAM_MN_dual2:inst6\|dout~78 3 COMB LCCOMB_X30_Y30_N14 1 " "Info: 3: + IC(0.581 ns) + CELL(0.053 ns) = 2.484 ns; Loc. = LCCOMB_X30_Y30_N14; Fanout = 1; COMB Node = 'RAM_MN_dual2:inst6\|dout~78'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.634 ns" { RAM_MN_dual2:inst6|altsyncram:ram_rtl_1|altsyncram_rmi1:auto_generated|q_b[0] RAM_MN_dual2:inst6|dout~78 } "NODE_NAME" } } { "RAM_MN_dual2.vhd" "" { Text "F:/111/fen_zu_interlacing/RAM_MN_dual2.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 2.639 ns RAM_MN_dual2:inst6\|dout 4 REG LCFF_X30_Y30_N15 2 " "Info: 4: + IC(0.000 ns) + CELL(0.155 ns) = 2.639 ns; Loc. = LCFF_X30_Y30_N15; Fanout = 2; REG Node = 'RAM_MN_dual2:inst6\|dout'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.155 ns" { RAM_MN_dual2:inst6|dout~78 RAM_MN_dual2:inst6|dout } "NODE_NAME" } } { "RAM_MN_dual2.vhd" "" { Text "F:/111/fen_zu_interlacing/RAM_MN_dual2.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.058 ns ( 77.98 % ) " "Info: Total cell delay = 2.058 ns ( 77.98 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.581 ns ( 22.02 % ) " "Info: Total interconnect delay = 0.581 ns ( 22.02 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.639 ns" { RAM_MN_dual2:inst6|altsyncram:ram_rtl_1|altsyncram_rmi1:auto_generated|ram_block1a0~portb_address_reg0 RAM_MN_dual2:inst6|altsyncram:ram_rtl_1|altsyncram_rmi1:auto_generated|q_b[0] RAM_MN_dual2:inst6|dout~78 RAM_MN_dual2:inst6|dout } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.639 ns" { RAM_MN_dual2:inst6|altsyncram:ram_rtl_1|altsyncram_rmi1:auto_generated|ram_block1a0~portb_address_reg0 RAM_MN_dual2:inst6|altsyncram:ram_rtl_1|altsyncram_rmi1:auto_generated|q_b[0] RAM_MN_dual2:inst6|dout~78 RAM_MN_dual2:inst6|dout } { 0.000ns 0.000ns 0.581ns 0.000ns } { 0.000ns 1.850ns 0.053ns 0.155ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.169 ns - Smallest " "Info: - Smallest clock skew is 0.169 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.944 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.944 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_P25 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_P25; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "interlace.bdf" "" { Schematic "F:/111/fen_zu_interlacing/interlace.bdf" { { -120 -104 64 -104 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.354 ns) + CELL(0.000 ns) 1.208 ns clk~clkctrl 2 COMB CLKCTRL_G1 58 " "Info: 2: + IC(0.354 ns) + CELL(0.000 ns) = 1.208 ns; Loc. = CLKCTRL_G1; Fanout = 58; COMB Node = 'clk~clkctrl'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.354 ns" { clk clk~clkctrl } "NODE_NAME" } } { "interlace.bdf" "" { Schematic "F:/111/fen_zu_interlacing/interlace.bdf" { { -120 -104 64 -104 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.118 ns) + CELL(0.618 ns) 2.944 ns RAM_MN_dual2:inst6\|dout 3 REG LCFF_X30_Y30_N15 2 " "Info: 3: + IC(1.118 ns) + CELL(0.618 ns) = 2.944 ns; Loc. = LCFF_X30_Y30_N15; Fanout = 2; REG Node = 'RAM_MN_dual2:inst6\|dout'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.736 ns" { clk~clkctrl RAM_MN_dual2:inst6|dout } "NODE_NAME" } } { "RAM_MN_dual2.vhd" "" { Text "F:/111/fen_zu_interlacing/RAM_MN_dual2.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 50.00 % ) " "Info: Total cell delay = 1.472 ns ( 50.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.472 ns ( 50.00 % ) " "Info: Total interconnect delay = 1.472 ns ( 50.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.944 ns" { clk clk~clkctrl RAM_MN_dual2:inst6|dout } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.944 ns" { clk clk~combout clk~clkctrl RAM_MN_dual2:inst6|dout } { 0.000ns 0.000ns 0.354ns 1.118ns } { 0.000ns 0.854ns 0.000ns 0.618ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.775 ns - Longest memory " "Info: - Longest clock path from clock \"clk\" to source memory is 2.775 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_P25 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_P25; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "interlace.bdf" "" { Schematic "F:/111/fen_zu_interlacing/interlace.bdf" { { -120 -104 64 -104 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.354 ns) + CELL(0.000 ns) 1.208 ns clk~clkctrl 2 COMB CLKCTRL_G1 58 " "Info: 2: + IC(0.354 ns) + CELL(0.000 ns) = 1.208 ns; Loc. = CLKCTRL_G1; Fanout = 58; COMB Node = 'clk~clkctrl'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.354 ns" { clk clk~clkctrl } "NODE_NAME" } } { "interlace.bdf" "" { Schematic "F:/111/fen_zu_interlacing/interlace.bdf" { { -120 -104 64 -104 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(0.467 ns) 2.775 ns RAM_MN_dual2:inst6\|altsyncram:ram_rtl_1\|altsyncram_rmi1:auto_generated\|ram_block1a0~portb_address_reg0 3 MEM M4K_X31_Y31 1 " "Info: 3: + IC(1.100 ns) + CELL(0.467 ns) = 2.775 ns; Loc. = M4K_X31_Y31; Fanout = 1; MEM Node = 'RAM_MN_dual2:inst6\|altsyncram:ram_rtl_1\|altsyncram_rmi1:auto_generated\|ram_block1a0~portb_address_reg0'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.567 ns" { clk~clkctrl RAM_MN_dual2:inst6|altsyncram:ram_rtl_1|altsyncram_rmi1:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } } { "db/altsyncram_rmi1.tdf" "" { Text "F:/111/fen_zu_interlacing/db/altsyncram_rmi1.tdf" 46 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.321 ns ( 47.60 % ) " "Info: Total cell delay = 1.321 ns ( 47.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.454 ns ( 52.40 % ) " "Info: Total interconnect delay = 1.454 ns ( 52.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.775 ns" { clk clk~clkctrl RAM_MN_dual2:inst6|altsyncram:ram_rtl_1|altsyncram_rmi1:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.775 ns" { clk clk~combout clk~clkctrl RAM_MN_dual2:inst6|altsyncram:ram_rtl_1|altsyncram_rmi1:auto_generated|ram_block1a0~portb_address_reg0 } { 0.000ns 0.000ns 0.354ns 1.100ns } { 0.000ns 0.854ns 0.000ns 0.467ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.944 ns" { clk clk~clkctrl RAM_MN_dual2:inst6|dout } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.944 ns" { clk clk~combout clk~clkctrl RAM_MN_dual2:inst6|dout } { 0.000ns 0.000ns 0.354ns 1.118ns } { 0.000ns 0.854ns 0.000ns 0.618ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.775 ns" { clk clk~clkctrl RAM_MN_dual2:inst6|altsyncram:ram_rtl_1|altsyncram_rmi1:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.775 ns" { clk clk~combout clk~clkctrl RAM_MN_dual2:inst6|altsyncram:ram_rtl_1|altsyncram_rmi1:auto_generated|ram_block1a0~portb_address_reg0 } { 0.000ns 0.000ns 0.354ns 1.100ns } { 0.000ns 0.854ns 0.000ns 0.467ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.136 ns + " "Info: + Micro clock to output delay of source is 0.136 ns" {  } { { "db/altsyncram_rmi1.tdf" "" { Text "F:/111/fen_zu_interlacing/db/altsyncram_rmi1.tdf" 46 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" {  } { { "RAM_MN_dual2.vhd" "" { Text "F:/111/fen_zu_interlacing/RAM_MN_dual2.vhd" 12 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.639 ns" { RAM_MN_dual2:inst6|altsyncram:ram_rtl_1|altsyncram_rmi1:auto_generated|ram_block1a0~portb_address_reg0 RAM_MN_dual2:inst6|altsyncram:ram_rtl_1|altsyncram_rmi1:auto_generated|q_b[0] RAM_MN_dual2:inst6|dout~78 RAM_MN_dual2:inst6|dout } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.639 ns" { RAM_MN_dual2:inst6|altsyncram:ram_rtl_1|altsyncram_rmi1:auto_generated|ram_block1a0~portb_address_reg0 RAM_MN_dual2:inst6|altsyncram:ram_rtl_1|altsyncram_rmi1:auto_generated|q_b[0] RAM_MN_dual2:inst6|dout~78 RAM_MN_dual2:inst6|dout } { 0.000ns 0.000ns 0.581ns 0.000ns } { 0.000ns 1.850ns 0.053ns 0.155ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.944 ns" { clk clk~clkctrl RAM_MN_dual2:inst6|dout } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.944 ns" { clk clk~combout clk~clkctrl RAM_MN_dual2:inst6|dout } { 0.000ns 0.000ns 0.354ns 1.118ns } { 0.000ns 0.854ns 0.000ns 0.618ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.775 ns" { clk clk~clkctrl RAM_MN_dual2:inst6|altsyncram:ram_rtl_1|altsyncram_rmi1:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.775 ns" { clk clk~combout clk~clkctrl RAM_MN_dual2:inst6|altsyncram:ram_rtl_1|altsyncram_rmi1:auto_generated|ram_block1a0~portb_address_reg0 } { 0.000ns 0.000ns 0.354ns 1.100ns } { 0.000ns 0.854ns 0.000ns 0.467ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk rw_control counter:inst8\|cnt\[4\] 8.291 ns register " "Info: tco from clock \"clk\" to destination pin \"rw_control\" through register \"counter:inst8\|cnt\[4\]\" is 8.291 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.930 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.930 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_P25 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_P25; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "interlace.bdf" "" { Schematic "F:/111/fen_zu_interlacing/interlace.bdf" { { -120 -104 64 -104 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.354 ns) + CELL(0.000 ns) 1.208 ns clk~clkctrl 2 COMB CLKCTRL_G1 58 " "Info: 2: + IC(0.354 ns) + CELL(0.000 ns) = 1.208 ns; Loc. = CLKCTRL_G1; Fanout = 58; COMB Node = 'clk~clkctrl'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.354 ns" { clk clk~clkctrl } "NODE_NAME" } } { "interlace.bdf" "" { Schematic "F:/111/fen_zu_interlacing/interlace.bdf" { { -120 -104 64 -104 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.104 ns) + CELL(0.618 ns) 2.930 ns counter:inst8\|cnt\[4\] 3 REG LCFF_X32_Y30_N23 4 " "Info: 3: + IC(1.104 ns) + CELL(0.618 ns) = 2.930 ns; Loc. = LCFF_X32_Y30_N23; Fanout = 4; REG Node = 'counter:inst8\|cnt\[4\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.722 ns" { clk~clkctrl counter:inst8|cnt[4] } "NODE_NAME" } } { "counter.v" "" { Text "F:/111/fen_zu_interlacing/counter.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 50.24 % ) " "Info: Total cell delay = 1.472 ns ( 50.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.458 ns ( 49.76 % ) " "Info: Total interconnect delay = 1.458 ns ( 49.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.930 ns" { clk clk~clkctrl counter:inst8|cnt[4] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.930 ns" { clk clk~combout clk~clkctrl counter:inst8|cnt[4] } { 0.000ns 0.000ns 0.354ns 1.104ns } { 0.000ns 0.854ns 0.000ns 0.618ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" {  } { { "counter.v" "" { Text "F:/111/fen_zu_interlacing/counter.v" 15 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.267 ns + Longest register pin " "Info: + Longest register to pin delay is 5.267 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter:inst8\|cnt\[4\] 1 REG LCFF_X32_Y30_N23 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X32_Y30_N23; Fanout = 4; REG Node = 'counter:inst8\|cnt\[4\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { counter:inst8|cnt[4] } "NODE_NAME" } } { "counter.v" "" { Text "F:/111/fen_zu_interlacing/counter.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.612 ns) + CELL(0.366 ns) 0.978 ns counter:inst8\|LessThan0~52 2 COMB LCCOMB_X30_Y30_N10 7 " "Info: 2: + IC(0.612 ns) + CELL(0.366 ns) = 0.978 ns; Loc. = LCCOMB_X30_Y30_N10; Fanout = 7; COMB Node = 'counter:inst8\|LessThan0~52'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.978 ns" { counter:inst8|cnt[4] counter:inst8|LessThan0~52 } "NODE_NAME" } } { "counter.v" "" { Text "F:/111/fen_zu_interlacing/counter.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.135 ns) + CELL(2.154 ns) 5.267 ns rw_control 3 PIN PIN_K26 0 " "Info: 3: + IC(2.135 ns) + CELL(2.154 ns) = 5.267 ns; Loc. = PIN_K26; Fanout = 0; PIN Node = 'rw_control'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.289 ns" { counter:inst8|LessThan0~52 rw_control } "NODE_NAME" } } { "interlace.bdf" "" { Schematic "F:/111/fen_zu_interlacing/interlace.bdf" { { -184 504 680 -168 "rw_control" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.520 ns ( 47.85 % ) " "Info: Total cell delay = 2.520 ns ( 47.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.747 ns ( 52.15 % ) " "Info: Total interconnect delay = 2.747 ns ( 52.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.267 ns" { counter:inst8|cnt[4] counter:inst8|LessThan0~52 rw_control } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "5.267 ns" { counter:inst8|cnt[4] counter:inst8|LessThan0~52 rw_control } { 0.000ns 0.612ns 2.135ns } { 0.000ns 0.366ns 2.154ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.930 ns" { clk clk~clkctrl counter:inst8|cnt[4] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.930 ns" { clk clk~combout clk~clkctrl counter:inst8|cnt[4] } { 0.000ns 0.000ns 0.354ns 1.104ns } { 0.000ns 0.854ns 0.000ns 0.618ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.267 ns" { counter:inst8|cnt[4] counter:inst8|LessThan0~52 rw_control } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "5.267 ns" { counter:inst8|cnt[4] counter:inst8|LessThan0~52 rw_control } { 0.000ns 0.612ns 2.135ns } { 0.000ns 0.366ns 2.154ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 07 22:23:15 2008 " "Info: Processing ended: Mon Apr 07 22:23:15 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}