jiaozhijiejiaozhi.tan.qmsg

一个简单的交织实现程序

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk memory interlace:inst\|RAM_MN_dual2:inst6\|altsyncram:ram_rtl_2\|altsyncram_1qe1:auto_generated\|ram_block1a0~portb_address_reg0 register interlace:inst\|RAM_MN_dual2:inst6\|dout 165.73 MHz 6.034 ns Internal " "Info: Clock \"clk\" has Internal fmax of 165.73 MHz between source memory \"interlace:inst\|RAM_MN_dual2:inst6\|altsyncram:ram_rtl_2\|altsyncram_1qe1:auto_generated\|ram_block1a0~portb_address_reg0\" and destination register \"interlace:inst\|RAM_MN_dual2:inst6\|dout\" (period= 6.034 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.952 ns + Longest memory register " "Info: + Longest memory to register delay is 2.952 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns interlace:inst\|RAM_MN_dual2:inst6\|altsyncram:ram_rtl_2\|altsyncram_1qe1:auto_generated\|ram_block1a0~portb_address_reg0 1 MEM M4K_X31_Y39 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X31_Y39; Fanout = 1; MEM Node = 'interlace:inst\|RAM_MN_dual2:inst6\|altsyncram:ram_rtl_2\|altsyncram_1qe1:auto_generated\|ram_block1a0~portb_address_reg0'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { interlace:inst|RAM_MN_dual2:inst6|altsyncram:ram_rtl_2|altsyncram_1qe1:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } } { "db/altsyncram_1qe1.tdf" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/db/altsyncram_1qe1.tdf" 47 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.130 ns) 2.130 ns interlace:inst\|RAM_MN_dual2:inst6\|altsyncram:ram_rtl_2\|altsyncram_1qe1:auto_generated\|q_b\[0\] 2 MEM M4K_X31_Y39 1 " "Info: 2: + IC(0.000 ns) + CELL(2.130 ns) = 2.130 ns; Loc. = M4K_X31_Y39; Fanout = 1; MEM Node = 'interlace:inst\|RAM_MN_dual2:inst6\|altsyncram:ram_rtl_2\|altsyncram_1qe1:auto_generated\|q_b\[0\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.130 ns" { interlace:inst|RAM_MN_dual2:inst6|altsyncram:ram_rtl_2|altsyncram_1qe1:auto_generated|ram_block1a0~portb_address_reg0 interlace:inst|RAM_MN_dual2:inst6|altsyncram:ram_rtl_2|altsyncram_1qe1:auto_generated|q_b[0] } "NODE_NAME" } } { "db/altsyncram_1qe1.tdf" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/db/altsyncram_1qe1.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.614 ns) + CELL(0.053 ns) 2.797 ns interlace:inst\|RAM_MN_dual2:inst6\|dout~29 3 COMB LCCOMB_X30_Y41_N30 1 " "Info: 3: + IC(0.614 ns) + CELL(0.053 ns) = 2.797 ns; Loc. = LCCOMB_X30_Y41_N30; Fanout = 1; COMB Node = 'interlace:inst\|RAM_MN_dual2:inst6\|dout~29'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.667 ns" { interlace:inst|RAM_MN_dual2:inst6|altsyncram:ram_rtl_2|altsyncram_1qe1:auto_generated|q_b[0] interlace:inst|RAM_MN_dual2:inst6|dout~29 } "NODE_NAME" } } { "RAM_MN_dual2.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/RAM_MN_dual2.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 2.952 ns interlace:inst\|RAM_MN_dual2:inst6\|dout 4 REG LCFF_X30_Y41_N31 2 " "Info: 4: + IC(0.000 ns) + CELL(0.155 ns) = 2.952 ns; Loc. = LCFF_X30_Y41_N31; Fanout = 2; REG Node = 'interlace:inst\|RAM_MN_dual2:inst6\|dout'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.155 ns" { interlace:inst|RAM_MN_dual2:inst6|dout~29 interlace:inst|RAM_MN_dual2:inst6|dout } "NODE_NAME" } } { "RAM_MN_dual2.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/RAM_MN_dual2.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.338 ns ( 79.20 % ) " "Info: Total cell delay = 2.338 ns ( 79.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.614 ns ( 20.80 % ) " "Info: Total interconnect delay = 0.614 ns ( 20.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.952 ns" { interlace:inst|RAM_MN_dual2:inst6|altsyncram:ram_rtl_2|altsyncram_1qe1:auto_generated|ram_block1a0~portb_address_reg0 interlace:inst|RAM_MN_dual2:inst6|altsyncram:ram_rtl_2|altsyncram_1qe1:auto_generated|q_b[0] interlace:inst|RAM_MN_dual2:inst6|dout~29 interlace:inst|RAM_MN_dual2:inst6|dout } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.952 ns" { interlace:inst|RAM_MN_dual2:inst6|altsyncram:ram_rtl_2|altsyncram_1qe1:auto_generated|ram_block1a0~portb_address_reg0 interlace:inst|RAM_MN_dual2:inst6|altsyncram:ram_rtl_2|altsyncram_1qe1:auto_generated|q_b[0] interlace:inst|RAM_MN_dual2:inst6|dout~29 interlace:inst|RAM_MN_dual2:inst6|dout } { 0.000ns 0.000ns 0.614ns 0.000ns } { 0.000ns 2.130ns 0.053ns 0.155ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.161 ns - Smallest " "Info: - Smallest clock skew is 0.161 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.934 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.934 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.844 ns) 0.844 ns clk 1 CLK PIN_P23 1 " "Info: 1: + IC(0.000 ns) + CELL(0.844 ns) = 0.844 ns; Loc. = PIN_P23; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "jiaozhijiejiaozhi.bdf" "" { Schematic "F:/liangshuo程序/1/fen_zu_interlacing/jiaozhijiejiaozhi.bdf" { { 104 -8 160 120 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.187 ns clk~clkctrl 2 COMB CLKCTRL_G3 82 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.187 ns; Loc. = CLKCTRL_G3; Fanout = 82; COMB Node = 'clk~clkctrl'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "jiaozhijiejiaozhi.bdf" "" { Schematic "F:/liangshuo程序/1/fen_zu_interlacing/jiaozhijiejiaozhi.bdf" { { 104 -8 160 120 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.129 ns) + CELL(0.618 ns) 2.934 ns interlace:inst\|RAM_MN_dual2:inst6\|dout 3 REG LCFF_X30_Y41_N31 2 " "Info: 3: + IC(1.129 ns) + CELL(0.618 ns) = 2.934 ns; Loc. = LCFF_X30_Y41_N31; Fanout = 2; REG Node = 'interlace:inst\|RAM_MN_dual2:inst6\|dout'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.747 ns" { clk~clkctrl interlace:inst|RAM_MN_dual2:inst6|dout } "NODE_NAME" } } { "RAM_MN_dual2.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/RAM_MN_dual2.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.462 ns ( 49.83 % ) " "Info: Total cell delay = 1.462 ns ( 49.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.472 ns ( 50.17 % ) " "Info: Total interconnect delay = 1.472 ns ( 50.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.934 ns" { clk clk~clkctrl interlace:inst|RAM_MN_dual2:inst6|dout } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.934 ns" { clk clk~combout clk~clkctrl interlace:inst|RAM_MN_dual2:inst6|dout } { 0.000ns 0.000ns 0.343ns 1.129ns } { 0.000ns 0.844ns 0.000ns 0.618ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.773 ns - Longest memory " "Info: - Longest clock path from clock \"clk\" to source memory is 2.773 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.844 ns) 0.844 ns clk 1 CLK PIN_P23 1 " "Info: 1: + IC(0.000 ns) + CELL(0.844 ns) = 0.844 ns; Loc. = PIN_P23; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "jiaozhijiejiaozhi.bdf" "" { Schematic "F:/liangshuo程序/1/fen_zu_interlacing/jiaozhijiejiaozhi.bdf" { { 104 -8 160 120 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.187 ns clk~clkctrl 2 COMB CLKCTRL_G3 82 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.187 ns; Loc. = CLKCTRL_G3; Fanout = 82; COMB Node = 'clk~clkctrl'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "jiaozhijiejiaozhi.bdf" "" { Schematic "F:/liangshuo程序/1/fen_zu_interlacing/jiaozhijiejiaozhi.bdf" { { 104 -8 160 120 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.119 ns) + CELL(0.467 ns) 2.773 ns interlace:inst\|RAM_MN_dual2:inst6\|altsyncram:ram_rtl_2\|altsyncram_1qe1:auto_generated\|ram_block1a0~portb_address_reg0 3 MEM M4K_X31_Y39 1 " "Info: 3: + IC(1.119 ns) + CELL(0.467 ns) = 2.773 ns; Loc. = M4K_X31_Y39; Fanout = 1; MEM Node = 'interlace:inst\|RAM_MN_dual2:inst6\|altsyncram:ram_rtl_2\|altsyncram_1qe1:auto_generated\|ram_block1a0~portb_address_reg0'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.586 ns" { clk~clkctrl interlace:inst|RAM_MN_dual2:inst6|altsyncram:ram_rtl_2|altsyncram_1qe1:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } } { "db/altsyncram_1qe1.tdf" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/db/altsyncram_1qe1.tdf" 47 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.311 ns ( 47.28 % ) " "Info: Total cell delay = 1.311 ns ( 47.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.462 ns ( 52.72 % ) " "Info: Total interconnect delay = 1.462 ns ( 52.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.773 ns" { clk clk~clkctrl interlace:inst|RAM_MN_dual2:inst6|altsyncram:ram_rtl_2|altsyncram_1qe1:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.773 ns" { clk clk~combout clk~clkctrl interlace:inst|RAM_MN_dual2:inst6|altsyncram:ram_rtl_2|altsyncram_1qe1:auto_generated|ram_block1a0~portb_address_reg0 } { 0.000ns 0.000ns 0.343ns 1.119ns } { 0.000ns 0.844ns 0.000ns 0.467ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.934 ns" { clk clk~clkctrl interlace:inst|RAM_MN_dual2:inst6|dout } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.934 ns" { clk clk~combout clk~clkctrl interlace:inst|RAM_MN_dual2:inst6|dout } { 0.000ns 0.000ns 0.343ns 1.129ns } { 0.000ns 0.844ns 0.000ns 0.618ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.773 ns" { clk clk~clkctrl interlace:inst|RAM_MN_dual2:inst6|altsyncram:ram_rtl_2|altsyncram_1qe1:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.773 ns" { clk clk~combout clk~clkctrl interlace:inst|RAM_MN_dual2:inst6|altsyncram:ram_rtl_2|altsyncram_1qe1:auto_generated|ram_block1a0~portb_address_reg0 } { 0.000ns 0.000ns 0.343ns 1.119ns } { 0.000ns 0.844ns 0.000ns 0.467ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.136 ns + " "Info: + Micro clock to output delay of source is 0.136 ns" {  } { { "db/altsyncram_1qe1.tdf" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/db/altsyncram_1qe1.tdf" 47 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" {  } { { "RAM_MN_dual2.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/RAM_MN_dual2.vhd" 12 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "db/altsyncram_1qe1.tdf" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/db/altsyncram_1qe1.tdf" 47 2 0 } } { "RAM_MN_dual2.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/RAM_MN_dual2.vhd" 12 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.952 ns" { interlace:inst|RAM_MN_dual2:inst6|altsyncram:ram_rtl_2|altsyncram_1qe1:auto_generated|ram_block1a0~portb_address_reg0 interlace:inst|RAM_MN_dual2:inst6|altsyncram:ram_rtl_2|altsyncram_1qe1:auto_generated|q_b[0] interlace:inst|RAM_MN_dual2:inst6|dout~29 interlace:inst|RAM_MN_dual2:inst6|dout } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.952 ns" { interlace:inst|RAM_MN_dual2:inst6|altsyncram:ram_rtl_2|altsyncram_1qe1:auto_generated|ram_block1a0~portb_address_reg0 interlace:inst|RAM_MN_dual2:inst6|altsyncram:ram_rtl_2|altsyncram_1qe1:auto_generated|q_b[0] interlace:inst|RAM_MN_dual2:inst6|dout~29 interlace:inst|RAM_MN_dual2:inst6|dout } { 0.000ns 0.000ns 0.614ns 0.000ns } { 0.000ns 2.130ns 0.053ns 0.155ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.934 ns" { clk clk~clkctrl interlace:inst|RAM_MN_dual2:inst6|dout } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.934 ns" { clk clk~combout clk~clkctrl interlace:inst|RAM_MN_dual2:inst6|dout } { 0.000ns 0.000ns 0.343ns 1.129ns } { 0.000ns 0.844ns 0.000ns 0.618ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.773 ns" { clk clk~clkctrl interlace:inst|RAM_MN_dual2:inst6|altsyncram:ram_rtl_2|altsyncram_1qe1:auto_generated|ram_block1a0~portb_address_reg0 } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.773 ns" { clk clk~combout clk~clkctrl interlace:inst|RAM_MN_dual2:inst6|altsyncram:ram_rtl_2|altsyncram_1qe1:auto_generated|ram_block1a0~portb_address_reg0 } { 0.000ns 0.000ns 0.343ns 1.119ns } { 0.000ns 0.844ns 0.000ns 0.467ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk output3 interlace:inst\|RAM_MN_dual:inst2\|dout 7.907 ns register " "Info: tco from clock \"clk\" to destination pin \"output3\" through register \"interlace:inst\|RAM_MN_dual:inst2\|dout\" is 7.907 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.934 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.934 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.844 ns) 0.844 ns clk 1 CLK PIN_P23 1 " "Info: 1: + IC(0.000 ns) + CELL(0.844 ns) = 0.844 ns; Loc. = PIN_P23; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "jiaozhijiejiaozhi.bdf" "" { Schematic "F:/liangshuo程序/1/fen_zu_interlacing/jiaozhijiejiaozhi.bdf" { { 104 -8 160 120 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.187 ns clk~clkctrl 2 COMB CLKCTRL_G3 82 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.187 ns; Loc. = CLKCTRL_G3; Fanout = 82; COMB Node = 'clk~clkctrl'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "jiaozhijiejiaozhi.bdf" "" { Schematic "F:/liangshuo程序/1/fen_zu_interlacing/jiaozhijiejiaozhi.bdf" { { 104 -8 160 120 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.129 ns) + CELL(0.618 ns) 2.934 ns interlace:inst\|RAM_MN_dual:inst2\|dout 3 REG LCFF_X30_Y41_N29 2 " "Info: 3: + IC(1.129 ns) + CELL(0.618 ns) = 2.934 ns; Loc. = LCFF_X30_Y41_N29; Fanout = 2; REG Node = 'interlace:inst\|RAM_MN_dual:inst2\|dout'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.747 ns" { clk~clkctrl interlace:inst|RAM_MN_dual:inst2|dout } "NODE_NAME" } } { "RAM_MN_dual.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/RAM_MN_dual.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.462 ns ( 49.83 % ) " "Info: Total cell delay = 1.462 ns ( 49.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.472 ns ( 50.17 % ) " "Info: Total interconnect delay = 1.472 ns ( 50.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.934 ns" { clk clk~clkctrl interlace:inst|RAM_MN_dual:inst2|dout } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.934 ns" { clk clk~combout clk~clkctrl interlace:inst|RAM_MN_dual:inst2|dout } { 0.000ns 0.000ns 0.343ns 1.129ns } { 0.000ns 0.844ns 0.000ns 0.618ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" {  } { { "RAM_MN_dual.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/RAM_MN_dual.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.879 ns + Longest register pin " "Info: + Longest register to pin delay is 4.879 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns interlace:inst\|RAM_MN_dual:inst2\|dout 1 REG LCFF_X30_Y41_N29 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X30_Y41_N29; Fanout = 2; REG Node = 'interlace:inst\|RAM_MN_dual:inst2\|dout'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { interlace:inst|RAM_MN_dual:inst2|dout } "NODE_NAME" } } { "RAM_MN_dual.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/RAM_MN_dual.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.273 ns) + CELL(0.346 ns) 0.619 ns interlace:inst\|cobination:inst3\|Add0~10 2 COMB LCCOMB_X30_Y41_N0 4 " "Info: 2: + IC(0.273 ns) + CELL(0.346 ns) = 0.619 ns; Loc. = LCCOMB_X30_Y41_N0; Fanout = 4; COMB Node = 'interlace:inst\|cobination:inst3\|Add0~10'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.619 ns" { interlace:inst|RAM_MN_dual:inst2|dout interlace:inst|cobination:inst3|Add0~10 } "NODE_NAME" } } { "cobination.v" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/cobination.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.136 ns) + CELL(2.124 ns) 4.879 ns output3 3 PIN PIN_H22 0 " "Info: 3: + IC(2.136 ns) + CELL(2.124 ns) = 4.879 ns; Loc. = PIN_H22; Fanout = 0; PIN Node = 'output3'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.260 ns" { interlace:inst|cobination:inst3|Add0~10 output3 } "NODE_NAME" } } { "jiaozhijiejiaozhi.bdf" "" { Schematic "F:/liangshuo程序/1/fen_zu_interlacing/jiaozhijiejiaozhi.bdf" { { 304 528 704 320 "output3" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.470 ns ( 50.63 % ) " "Info: Total cell delay = 2.470 ns ( 50.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.409 ns ( 49.37 % ) " "Info: Total interconnect delay = 2.409 ns ( 49.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.879 ns" { interlace:inst|RAM_MN_dual:inst2|dout interlace:inst|cobination:inst3|Add0~10 output3 } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "4.879 ns" { interlace:inst|RAM_MN_dual:inst2|dout interlace:inst|cobination:inst3|Add0~10 output3 } { 0.000ns 0.273ns 2.136ns } { 0.000ns 0.346ns 2.124ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.934 ns" { clk clk~clkctrl interlace:inst|RAM_MN_dual:inst2|dout } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.934 ns" { clk clk~combout clk~clkctrl interlace:inst|RAM_MN_dual:inst2|dout } { 0.000ns 0.000ns 0.343ns 1.129ns } { 0.000ns 0.844ns 0.000ns 0.618ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.879 ns" { interlace:inst|RAM_MN_dual:inst2|dout interlace:inst|cobination:inst3|Add0~10 output3 } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "4.879 ns" { interlace:inst|RAM_MN_dual:inst2|dout interlace:inst|cobination:inst3|Add0~10 output3 } { 0.000ns 0.273ns 2.136ns } { 0.000ns 0.346ns 2.124ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 09 12:11:37 2008 " "Info: Processing ended: Wed Apr 09 12:11:37 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}