jiaozhijiejiaozhi.hier_info

一个简单的交织实现程序

d1d2 <= Add0.DB_MAX_OUTPUT_PORT_TYPE
flag3 => flag4.DATAIN
flag4 <= flag3.DB_MAX_OUTPUT_PORT_TYPE


|jiaozhijiejiaozhi|interlace:inst
d1 <= RAM_MN_dual:inst2.dout
clk => RAM_MN_dual:inst2.CLK
clk => counter1:inst5.clk
clk => source:inst1.clk
clk => rom_mn_interlace:inst.clk
clk => rom_mn_seq:inst9.clk
clk => RAM_MN_dual2:inst6.CLK
clk => inst4.IN0
clk => inst8.CLK
d2 <= RAM_MN_dual2:inst6.dout
dataout <= cobination:inst3.d1d2
rw_control <= counter1:inst5.ch
source_out <= source:inst1.dataout
flag <= RAM_MN_dual:inst2.flag
flag4 <= inst7.DB_MAX_OUTPUT_PORT_TYPE
dataout1 <= inst8.DB_MAX_OUTPUT_PORT_TYPE
cnt4 <= counter1:inst5.series_addr[4]
cnt3 <= counter1:inst5.series_addr[3]
cnt2 <= counter1:inst5.series_addr[2]
cnt1 <= counter1:inst5.series_addr[1]
cnt0 <= counter1:inst5.series_addr[0]
cnt14 <= rom_mn_interlace:inst.interlace_addr[4]
cnt13 <= rom_mn_interlace:inst.interlace_addr[3]
cnt12 <= rom_mn_interlace:inst.interlace_addr[2]
cnt11 <= rom_mn_interlace:inst.interlace_addr[1]
cnt10 <= rom_mn_interlace:inst.interlace_addr[0]
cnt24 <= rom_mn_seq:inst9.seq_addr[4]
cnt23 <= rom_mn_seq:inst9.seq_addr[3]
cnt22 <= rom_mn_seq:inst9.seq_addr[2]
cnt21 <= rom_mn_seq:inst9.seq_addr[1]
cnt20 <= rom_mn_seq:inst9.seq_addr[0]


|jiaozhijiejiaozhi|interlace:inst|RAM_MN_dual:inst2
wr_addr[0] => Decoder0.IN4
wr_addr[1] => Decoder0.IN3
wr_addr[2] => Decoder0.IN2
wr_addr[3] => Decoder0.IN1
wr_addr[4] => Decoder0.IN0
re_addr[0] => Mux0.IN6
re_addr[1] => Mux0.IN5
re_addr[2] => Mux0.IN4
re_addr[3] => Mux0.IN3
re_addr[4] => Mux0.IN2
CLK => dout~reg0.CLK
CLK => flag1.CLK
CLK => ram[29].CLK
CLK => ram[28].CLK
CLK => ram[27].CLK
CLK => ram[26].CLK
CLK => ram[25].CLK
CLK => ram[24].CLK
CLK => ram[23].CLK
CLK => ram[22].CLK
CLK => ram[21].CLK
CLK => ram[20].CLK
CLK => ram[19].CLK
CLK => ram[18].CLK
CLK => ram[17].CLK
CLK => ram[16].CLK
CLK => ram[15].CLK
CLK => ram[14].CLK
CLK => ram[13].CLK
CLK => ram[12].CLK
CLK => ram[11].CLK
CLK => ram[10].CLK
CLK => ram[9].CLK
CLK => ram[8].CLK
CLK => ram[7].CLK
CLK => ram[6].CLK
CLK => ram[5].CLK
CLK => ram[4].CLK
CLK => ram[3].CLK
CLK => ram[2].CLK
CLK => ram[1].CLK
CLK => ram[0].CLK
CH => dout~0.OUTPUTSELECT
CH => flag1.DATAIN
din => ram[29].DATAIN
din => ram[28].DATAIN
din => ram[27].DATAIN
din => ram[26].DATAIN
din => ram[25].DATAIN
din => ram[24].DATAIN
din => ram[23].DATAIN
din => ram[22].DATAIN
din => ram[21].DATAIN
din => ram[20].DATAIN
din => ram[19].DATAIN
din => ram[18].DATAIN
din => ram[17].DATAIN
din => ram[16].DATAIN
din => ram[15].DATAIN
din => ram[14].DATAIN
din => ram[13].DATAIN
din => ram[12].DATAIN
din => ram[11].DATAIN
din => ram[10].DATAIN
din => ram[9].DATAIN
din => ram[8].DATAIN
din => ram[7].DATAIN
din => ram[6].DATAIN
din => ram[5].DATAIN
din => ram[4].DATAIN
din => ram[3].DATAIN
din => ram[2].DATAIN
din => ram[1].DATAIN
din => ram[0].DATAIN
flag <= flag~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout <= dout~reg0.DB_MAX_OUTPUT_PORT_TYPE


|jiaozhijiejiaozhi|interlace:inst|counter1:inst5
clk => series_addr[3]~reg0.CLK
clk => series_addr[2]~reg0.CLK
clk => series_addr[1]~reg0.CLK
clk => series_addr[0]~reg0.CLK
clk => cnt[5].CLK
clk => cnt[4].CLK
clk => cnt[3].CLK
clk => cnt[2].CLK
clk => cnt[1].CLK
clk => cnt[0].CLK
clk => series_addr[4]~reg0.CLK
series_addr[0] <= series_addr[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
series_addr[1] <= series_addr[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
series_addr[2] <= series_addr[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
series_addr[3] <= series_addr[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
series_addr[4] <= series_addr[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ch <= LessThan0.DB_MAX_OUTPUT_PORT_TYPE


|jiaozhijiejiaozhi|interlace:inst|source:inst1
clk => dataout~reg0.CLK
clk => m[0].CLK
clk => m[1].CLK
clk => m[2].CLK
clk => m[3].CLK
dataout <= dataout~reg0.DB_MAX_OUTPUT_PORT_TYPE


|jiaozhijiejiaozhi|interlace:inst|rom_mn_interlace:inst
counter[0] => Mux0.IN36
counter[0] => Mux1.IN36
counter[0] => Mux2.IN36
counter[0] => Mux3.IN36
counter[0] => Mux4.IN36
counter[1] => Mux0.IN35
counter[1] => Mux1.IN35
counter[1] => Mux2.IN35
counter[1] => Mux3.IN35
counter[1] => Mux4.IN35
counter[2] => Mux0.IN34
counter[2] => Mux1.IN34
counter[2] => Mux2.IN34
counter[2] => Mux3.IN34
counter[2] => Mux4.IN34
counter[3] => Mux0.IN33
counter[3] => Mux1.IN33
counter[3] => Mux2.IN33
counter[3] => Mux3.IN33
counter[3] => Mux4.IN33
counter[4] => Mux0.IN32
counter[4] => Mux1.IN32
counter[4] => Mux2.IN32
counter[4] => Mux3.IN32
counter[4] => Mux4.IN32
clk => interlace_addr[0]~reg0.CLK
clk => interlace_addr[1]~reg0.CLK
clk => interlace_addr[2]~reg0.CLK
clk => interlace_addr[3]~reg0.CLK
clk => interlace_addr[4]~reg0.CLK
interlace_addr[0] <= interlace_addr[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
interlace_addr[1] <= interlace_addr[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
interlace_addr[2] <= interlace_addr[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
interlace_addr[3] <= interlace_addr[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
interlace_addr[4] <= interlace_addr[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|jiaozhijiejiaozhi|interlace:inst|rom_mn_seq:inst9
counter[0] => seq_addr[0]~reg0.DATAIN
counter[1] => seq_addr[1]~reg0.DATAIN
counter[2] => seq_addr[2]~reg0.DATAIN
counter[3] => seq_addr[3]~reg0.DATAIN
counter[4] => seq_addr[4]~reg0.DATAIN
clk => seq_addr[0]~reg0.CLK
clk => seq_addr[1]~reg0.CLK
clk => seq_addr[2]~reg0.CLK
clk => seq_addr[3]~reg0.CLK
clk => seq_addr[4]~reg0.CLK
seq_addr[0] <= seq_addr[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
seq_addr[1] <= seq_addr[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
seq_addr[2] <= seq_addr[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
seq_addr[3] <= seq_addr[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
seq_addr[4] <= seq_addr[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|jiaozhijiejiaozhi|interlace:inst|RAM_MN_dual2:inst6
wr_addr[0] => Decoder0.IN4
wr_addr[1] => Decoder0.IN3
wr_addr[2] => Decoder0.IN2
wr_addr[3] => Decoder0.IN1
wr_addr[4] => Decoder0.IN0
re_addr[0] => Mux0.IN6
re_addr[1] => Mux0.IN5
re_addr[2] => Mux0.IN4
re_addr[3] => Mux0.IN3
re_addr[4] => Mux0.IN2
CLK => dout~reg0.CLK
CLK => ram[29].CLK
CLK => ram[28].CLK
CLK => ram[27].CLK
CLK => ram[26].CLK
CLK => ram[25].CLK
CLK => ram[24].CLK
CLK => ram[23].CLK
CLK => ram[22].CLK
CLK => ram[21].CLK
CLK => ram[20].CLK
CLK => ram[19].CLK
CLK => ram[18].CLK
CLK => ram[17].CLK
CLK => ram[16].CLK
CLK => ram[15].CLK
CLK => ram[14].CLK
CLK => ram[13].CLK
CLK => ram[12].CLK
CLK => ram[11].CLK
CLK => ram[10].CLK
CLK => ram[9].CLK
CLK => ram[8].CLK
CLK => ram[7].CLK
CLK => ram[6].CLK
CLK => ram[5].CLK
CLK => ram[4].CLK
CLK => ram[3].CLK
CLK => ram[2].CLK
CLK => ram[1].CLK
CLK => ram[0].CLK
CH => dout~0.OUTPUTSELECT
din => ram[29].DATAIN
din => ram[28].DATAIN
din => ram[27].DATAIN
din => ram[26].DATAIN
din => ram[25].DATAIN
din => ram[24].DATAIN
din => ram[23].DATAIN
din => ram[22].DATAIN
din => ram[21].DATAIN
din => ram[20].DATAIN
din => ram[19].DATAIN
din => ram[18].DATAIN
din => ram[17].DATAIN
din => ram[16].DATAIN
din => ram[15].DATAIN
din => ram[14].DATAIN
din => ram[13].DATAIN
din => ram[12].DATAIN
din => ram[11].DATAIN
din => ram[10].DATAIN
din => ram[9].DATAIN
din => ram[8].DATAIN
din => ram[7].DATAIN
din => ram[6].DATAIN
din => ram[5].DATAIN
din => ram[4].DATAIN
din => ram[3].DATAIN
din => ram[2].DATAIN
din => ram[1].DATAIN
din => ram[0].DATAIN
dout <= dout~reg0.DB_MAX_OUTPUT_PORT_TYPE


|jiaozhijiejiaozhi|interlace:inst|cobination:inst3
d1 => Add0.IN1
d2 => Add0.IN2
d1d2 <= Add0.DB_MAX_OUTPUT_PORT_TYPE
flag3 => flag4.DATAIN
flag4 <= flag3.DB_MAX_OUTPUT_PORT_TYPE