jieinterlace.map.qmsg

来自「一个简单的交织实现程序」· QMSG 代码 · 共 50 行 · 第 1/3 页

{ "Warning" "WSGN_SEARCH_FILE" "source.vhd 2 1 " "Warning: Using design file source.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 source-a " "Info: Found design unit 1: source-a" {  } { { "source.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/source.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 source " "Info: Found entity 1: source" {  } { { "source.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/source.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "source interlace:inst\|source:inst1 " "Info: Elaborating entity \"source\" for hierarchy \"interlace:inst\|source:inst1\"" {  } { { "interlace.bdf" "inst1" { Schematic "F:/liangshuo程序/1/fen_zu_interlacing/interlace.bdf" { { -144 144 240 -48 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "interlace:inst\|rom_mn_interlace:inst\|interlace_addr\[0\] interlace:inst\|rom_mn_seq:inst9\|seq_addr\[0\] " "Info: Duplicate register \"interlace:inst\|rom_mn_interlace:inst\|interlace_addr\[0\]\" merged to single register \"interlace:inst\|rom_mn_seq:inst9\|seq_addr\[0\]\"" {  } { { "rom_mn_interlace.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/rom_mn_interlace.vhd" 62 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "jieinterlace:inst2\|rom_mn_interlace:inst\|interlace_addr\[0\] jieinterlace:inst2\|rom_mn_seq:inst9\|seq_addr\[0\] " "Info: Duplicate register \"jieinterlace:inst2\|rom_mn_interlace:inst\|interlace_addr\[0\]\" merged to single register \"jieinterlace:inst2\|rom_mn_seq:inst9\|seq_addr\[0\]\"" {  } { { "rom_mn_interlace.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/rom_mn_interlace.vhd" 62 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "jieinterlace:inst2\|rom_mn_seq:inst9\|seq_addr\[0\] interlace:inst\|rom_mn_seq:inst9\|seq_addr\[0\] " "Info: Duplicate register \"jieinterlace:inst2\|rom_mn_seq:inst9\|seq_addr\[0\]\" merged to single register \"interlace:inst\|rom_mn_seq:inst9\|seq_addr\[0\]\"" {  } { { "rom_mn_seq.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/rom_mn_seq.vhd" 54 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "jieinterlace:inst2\|rom_mn_seq:inst9\|seq_addr\[1\] interlace:inst\|rom_mn_seq:inst9\|seq_addr\[1\] " "Info: Duplicate register \"jieinterlace:inst2\|rom_mn_seq:inst9\|seq_addr\[1\]\" merged to single register \"interlace:inst\|rom_mn_seq:inst9\|seq_addr\[1\]\"" {  } { { "rom_mn_seq.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/rom_mn_seq.vhd" 54 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "jieinterlace:inst2\|rom_mn_seq:inst9\|seq_addr\[2\] interlace:inst\|rom_mn_seq:inst9\|seq_addr\[2\] " "Info: Duplicate register \"jieinterlace:inst2\|rom_mn_seq:inst9\|seq_addr\[2\]\" merged to single register \"interlace:inst\|rom_mn_seq:inst9\|seq_addr\[2\]\"" {  } { { "rom_mn_seq.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/rom_mn_seq.vhd" 54 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "jieinterlace:inst2\|rom_mn_seq:inst9\|seq_addr\[3\] interlace:inst\|rom_mn_seq:inst9\|seq_addr\[3\] " "Info: Duplicate register \"jieinterlace:inst2\|rom_mn_seq:inst9\|seq_addr\[3\]\" merged to single register \"interlace:inst\|rom_mn_seq:inst9\|seq_addr\[3\]\"" {  } { { "rom_mn_seq.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/rom_mn_seq.vhd" 54 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "jieinterlace:inst2\|rom_mn_seq:inst9\|seq_addr\[4\] interlace:inst\|rom_mn_seq:inst9\|seq_addr\[4\] " "Info: Duplicate register \"jieinterlace:inst2\|rom_mn_seq:inst9\|seq_addr\[4\]\" merged to single register \"interlace:inst\|rom_mn_seq:inst9\|seq_addr\[4\]\"" {  } { { "rom_mn_seq.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/rom_mn_seq.vhd" 54 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "jieinterlace:inst2\|counter:inst8\|series_addr\[3\] interlace:inst\|counter:inst8\|series_addr\[3\] " "Info: Duplicate register \"jieinterlace:inst2\|counter:inst8\|series_addr\[3\]\" merged to single register \"interlace:inst\|counter:inst8\|series_addr\[3\]\"" {  } { { "counter.v" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/counter.v" 9 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "jieinterlace:inst2\|counter:inst8\|series_addr\[2\] interlace:inst\|counter:inst8\|series_addr\[2\] " "Info: Duplicate register \"jieinterlace:inst2\|counter:inst8\|series_addr\[2\]\" merged to single register \"interlace:inst\|counter:inst8\|series_addr\[2\]\"" {  } { { "counter.v" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/counter.v" 9 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "jieinterlace:inst2\|counter:inst8\|series_addr\[1\] interlace:inst\|counter:inst8\|series_addr\[1\] " "Info: Duplicate register \"jieinterlace:inst2\|counter:inst8\|series_addr\[1\]\" merged to single register \"interlace:inst\|counter:inst8\|series_addr\[1\]\"" {  } { { "counter.v" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/counter.v" 9 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "jieinterlace:inst2\|counter:inst8\|series_addr\[0\] interlace:inst\|counter:inst8\|series_addr\[0\] " "Info: Duplicate register \"jieinterlace:inst2\|counter:inst8\|series_addr\[0\]\" merged to single register \"interlace:inst\|counter:inst8\|series_addr\[0\]\"" {  } { { "counter.v" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/counter.v" 9 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "jieinterlace:inst2\|counter:inst8\|cnt\[5\] interlace:inst\|counter:inst8\|cnt\[5\] " "Info: Duplicate register \"jieinterlace:inst2\|counter:inst8\|cnt\[5\]\" merged to single register \"interlace:inst\|counter:inst8\|cnt\[5\]\"" {  } { { "counter.v" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/counter.v" 15 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "jieinterlace:inst2\|counter:inst8\|cnt\[4\] interlace:inst\|counter:inst8\|cnt\[4\] " "Info: Duplicate register \"jieinterlace:inst2\|counter:inst8\|cnt\[4\]\" merged to single register \"interlace:inst\|counter:inst8\|cnt\[4\]\"" {  } { { "counter.v" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/counter.v" 15 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "jieinterlace:inst2\|counter:inst8\|cnt\[3\] interlace:inst\|counter:inst8\|cnt\[3\] " "Info: Duplicate register \"jieinterlace:inst2\|counter:inst8\|cnt\[3\]\" merged to single register \"interlace:inst\|counter:inst8\|cnt\[3\]\"" {  } { { "counter.v" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/counter.v" 15 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "jieinterlace:inst2\|counter:inst8\|cnt\[2\] interlace:inst\|counter:inst8\|cnt\[2\] " "Info: Duplicate register \"jieinterlace:inst2\|counter:inst8\|cnt\[2\]\" merged to single register \"interlace:inst\|counter:inst8\|cnt\[2\]\"" {  } { { "counter.v" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/counter.v" 15 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "jieinterlace:inst2\|counter:inst8\|cnt\[1\] interlace:inst\|counter:inst8\|cnt\[1\] " "Info: Duplicate register \"jieinterlace:inst2\|counter:inst8\|cnt\[1\]\" merged to single register \"interlace:inst\|counter:inst8\|cnt\[1\]\"" {  } { { "counter.v" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/counter.v" 15 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "jieinterlace:inst2\|counter:inst8\|cnt\[0\] interlace:inst\|counter:inst8\|cnt\[0\] " "Info: Duplicate register \"jieinterlace:inst2\|counter:inst8\|cnt\[0\]\" merged to single register \"interlace:inst\|counter:inst8\|cnt\[0\]\"" {  } { { "counter.v" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/counter.v" 15 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "jieinterlace:inst2\|counter:inst8\|series_addr\[4\] interlace:inst\|counter:inst8\|series_addr\[4\] " "Info: Duplicate register \"jieinterlace:inst2\|counter:inst8\|series_addr\[4\]\" merged to single register \"interlace:inst\|counter:inst8\|series_addr\[4\]\"" {  } { { "counter.v" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/counter.v" 9 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "jieinterlace:inst2\|rom_mn_interlace:inst\|interlace_addr\[1\] interlace:inst\|rom_mn_interlace:inst\|interlace_addr\[1\] " "Info: Duplicate register \"jieinterlace:inst2\|rom_mn_interlace:inst\|interlace_addr\[1\]\" merged to single register \"interlace:inst\|rom_mn_interlace:inst\|interlace_addr\[1\]\"" {  } { { "rom_mn_interlace.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/rom_mn_interlace.vhd" 62 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "jieinterlace:inst2\|rom_mn_interlace:inst\|interlace_addr\[2\] interlace:inst\|rom_mn_interlace:inst\|interlace_addr\[2\] " "Info: Duplicate register \"jieinterlace:inst2\|rom_mn_interlace:inst\|interlace_addr\[2\]\" merged to single register \"interlace:inst\|rom_mn_interlace:inst\|interlace_addr\[2\]\"" {  } { { "rom_mn_interlace.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/rom_mn_interlace.vhd" 62 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "jieinterlace:inst2\|rom_mn_interlace:inst\|interlace_addr\[3\] interlace:inst\|rom_mn_interlace:inst\|interlace_addr\[3\] " "Info: Duplicate register \"jieinterlace:inst2\|rom_mn_interlace:inst\|interlace_addr\[3\]\" merged to single register \"interlace:inst\|rom_mn_interlace:inst\|interlace_addr\[3\]\"" {  } { { "rom_mn_interlace.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/rom_mn_interlace.vhd" 62 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "jieinterlace:inst2\|rom_mn_interlace:inst\|interlace_addr\[4\] interlace:inst\|rom_mn_interlace:inst\|interlace_addr\[4\] " "Info: Duplicate register \"jieinterlace:inst2\|rom_mn_interlace:inst\|interlace_addr\[4\]\" merged to single register \"interlace:inst\|rom_mn_interlace:inst\|interlace_addr\[4\]\"" {  } { { "rom_mn_interlace.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/rom_mn_interlace.vhd" 62 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Warning" "WOPT_RAM_PASS_THROUGH_LOGIC_INSERTED_ALTSYNCRAM" "jieinterlace:inst2\|RAM_MN_dual2:inst6\|ram\[0\]~60 " "Warning: Created node \"jieinterlace:inst2\|RAM_MN_dual2:inst6\|ram\[0\]~60\" as a RAM by generating altsyncram megafunction to implement register logic with M512 or M4K memory block or M-RAM. Pass-through logic has been added." {  } { { "RAM_MN_dual2.vhd" "ram\[0\]~60" { Text "F:/liangshuo程序/1/fen_zu_interlacing/RAM_MN_dual2.vhd" 27 -1 0 } }  } 0 0 "Created node \"%1!s!\" as a RAM by generating altsyncram megafunction to implement register logic with M512 or M4K memory block or M-RAM. Pass-through logic has been added." 0 0}
{ "Warning" "WOPT_RAM_PASS_THROUGH_LOGIC_INSERTED_ALTSYNCRAM" "jieinterlace:inst2\|RAM_MN_dual:inst5\|ram\[0\]~60 " "Warning: Created node \"jieinterlace:inst2\|RAM_MN_dual:inst5\|ram\[0\]~60\" as a RAM by generating altsyncram megafunction to implement register logic with M512 or M4K memory block or M-RAM. Pass-through logic has been added." {  } { { "RAM_MN_dual.vhd" "ram\[0\]~60" { Text "F:/liangshuo程序/1/fen_zu_interlacing/RAM_MN_dual.vhd" 27 -1 0 } }  } 0 0 "Created node \"%1!s!\" as a RAM by generating altsyncram megafunction to implement register logic with M512 or M4K memory block or M-RAM. Pass-through logic has been added." 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "jieinterlace:inst2\|RAM_MN_dual2:inst6\|Mux0~49 interlace:inst\|rom_mn_seq:inst9\|seq_addr\[0\] " "Info: Duplicate register \"jieinterlace:inst2\|RAM_MN_dual2:inst6\|Mux0~49\" merged to single register \"interlace:inst\|rom_mn_seq:inst9\|seq_addr\[0\]\"" {  } { { "RAM_MN_dual2.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/RAM_MN_dual2.vhd" 32 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "jieinterlace:inst2\|RAM_MN_dual:inst5\|Mux0~49 interlace:inst\|rom_mn_seq:inst9\|seq_addr\[0\] " "Info: Duplicate register \"jieinterlace:inst2\|RAM_MN_dual:inst5\|Mux0~49\" merged to single register \"interlace:inst\|rom_mn_seq:inst9\|seq_addr\[0\]\"" {  } { { "RAM_MN_dual.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/RAM_MN_dual.vhd" 32 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "jieinterlace:inst2\|RAM_MN_dual:inst5\|Mux0~48 jieinterlace:inst2\|RAM_MN_dual2:inst6\|Mux0~48 " "Info: Duplicate register \"jieinterlace:inst2\|RAM_MN_dual:inst5\|Mux0~48\" merged to single register \"jieinterlace:inst2\|RAM_MN_dual2:inst6\|Mux0~48\"" {  } { { "RAM_MN_dual.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/RAM_MN_dual.vhd" 32 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "jieinterlace:inst2\|RAM_MN_dual:inst5\|Mux0~51 jieinterlace:inst2\|RAM_MN_dual2:inst6\|Mux0~51 " "Info: Duplicate register \"jieinterlace:inst2\|RAM_MN_dual:inst5\|Mux0~51\" merged to single register \"jieinterlace:inst2\|RAM_MN_dual2:inst6\|Mux0~51\"" {  } { { "RAM_MN_dual.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/RAM_MN_dual.vhd" 32 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "jieinterlace:inst2\|RAM_MN_dual:inst5\|Mux0~52 jieinterlace:inst2\|RAM_MN_dual2:inst6\|Mux0~52 " "Info: Duplicate register \"jieinterlace:inst2\|RAM_MN_dual:inst5\|Mux0~52\" merged to single register \"jieinterlace:inst2\|RAM_MN_dual2:inst6\|Mux0~52\"" {  } { { "RAM_MN_dual.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/RAM_MN_dual.vhd" 32 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "jieinterlace:inst2\|RAM_MN_dual:inst5\|Mux0~54 jieinterlace:inst2\|RAM_MN_dual2:inst6\|Mux0~54 " "Info: Duplicate register \"jieinterlace:inst2\|RAM_MN_dual:inst5\|Mux0~54\" merged to single register \"jieinterlace:inst2\|RAM_MN_dual2:inst6\|Mux0~54\"" {  } { { "RAM_MN_dual.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/RAM_MN_dual.vhd" 32 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "jieinterlace:inst2\|RAM_MN_dual:inst5\|Mux0~55 jieinterlace:inst2\|RAM_MN_dual2:inst6\|Mux0~55 " "Info: Duplicate register \"jieinterlace:inst2\|RAM_MN_dual:inst5\|Mux0~55\" merged to single register \"jieinterlace:inst2\|RAM_MN_dual2:inst6\|Mux0~55\"" {  } { { "RAM_MN_dual.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/RAM_MN_dual.vhd" 32 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "jieinterlace:inst2\|RAM_MN_dual:inst5\|Mux0~57 jieinterlace:inst2\|RAM_MN_dual2:inst6\|Mux0~57 " "Info: Duplicate register \"jieinterlace:inst2\|RAM_MN_dual:inst5\|Mux0~57\" merged to single register \"jieinterlace:inst2\|RAM_MN_dual2:inst6\|Mux0~57\"" {  } { { "RAM_MN_dual.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/RAM_MN_dual.vhd" 32 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "jieinterlace:inst2\|RAM_MN_dual:inst5\|Mux0~58 jieinterlace:inst2\|RAM_MN_dual2:inst6\|Mux0~58 " "Info: Duplicate register \"jieinterlace:inst2\|RAM_MN_dual:inst5\|Mux0~58\" merged to single register \"jieinterlace:inst2\|RAM_MN_dual2:inst6\|Mux0~58\"" {  } { { "RAM_MN_dual.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/RAM_MN_dual.vhd" 32 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "jieinterlace:inst2\|RAM_MN_dual:inst5\|Mux0~60 jieinterlace:inst2\|RAM_MN_dual2:inst6\|Mux0~60 " "Info: Duplicate register \"jieinterlace:inst2\|RAM_MN_dual:inst5\|Mux0~60\" merged to single register \"jieinterlace:inst2\|RAM_MN_dual2:inst6\|Mux0~60\"" {  } { { "RAM_MN_dual.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/RAM_MN_dual.vhd" 32 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "jieinterlace:inst2\|RAM_MN_dual:inst5\|Mux0~61 jieinterlace:inst2\|RAM_MN_dual2:inst6\|Mux0~61 " "Info: Duplicate register \"jieinterlace:inst2\|RAM_MN_dual:inst5\|Mux0~61\" merged to single register \"jieinterlace:inst2\|RAM_MN_dual2:inst6\|Mux0~61\"" {  } { { "RAM_MN_dual.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/RAM_MN_dual.vhd" 32 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "jieinterlace:inst2\|RAM_MN_dual:inst5\|Mux0~63 jieinterlace:inst2\|RAM_MN_dual2:inst6\|Mux0~63 " "Info: Duplicate register \"jieinterlace:inst2\|RAM_MN_dual:inst5\|Mux0~63\" merged to single register \"jieinterlace:inst2\|RAM_MN_dual2:inst6\|Mux0~63\"" {  } { { "RAM_MN_dual.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/RAM_MN_dual.vhd" 32 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "jieinterlace:inst2\|RAM_MN_dual:inst5\|Mux0~65 jieinterlace:inst2\|RAM_MN_dual2:inst6\|Mux0~65 " "Info: Duplicate register \"jieinterlace:inst2\|RAM_MN_dual:inst5\|Mux0~65\" merged to single register \"jieinterlace:inst2\|RAM_MN_dual2:inst6\|Mux0~65\"" {  } { { "RAM_MN_dual.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/RAM_MN_dual.vhd" 32 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "interlace:inst\|source:inst1\|m\[0\] interlace:inst\|counter:inst8\|series_addr\[0\] " "Info: Duplicate register \"interlace:inst\|source:inst1\|m\[0\]\" merged to single register \"interlace:inst\|counter:inst8\|series_addr\[0\]\"" {  } { { "source.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/source.vhd" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "interlace:inst\|counter:inst8\|cnt\[0\] interlace:inst\|counter:inst8\|series_addr\[0\] " "Info: Duplicate register \"interlace:inst\|counter:inst8\|cnt\[0\]\" merged to single register \"interlace:inst\|counter:inst8\|series_addr\[0\]\"" {  } { { "counter.v" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/counter.v" 15 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "interlace:inst\|source:inst1\|m\[1\] interlace:inst\|counter:inst8\|cnt\[1\] " "Info: Duplicate register \"interlace:inst\|source:inst1\|m\[1\]\" merged to single register \"interlace:inst\|counter:inst8\|cnt\[1\]\"" {  } { { "source.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/source.vhd" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "2 " "Info: Inferred 2 megafunctions from design logic" { { "Info" "IOPT_ALTSYNCRAM_INFERRED" "jieinterlace:inst2\|RAM_MN_dual2:inst6\|ram\[0\]~60 32 2 " "Info: Inferred altsyncram megafunction (NUMWORDS_A=32, WIDTH_A=2) from the following design logic: \"jieinterlace:inst2\|RAM_MN_dual2:inst6\|ram\[0\]~60\"" {  } { { "RAM_MN_dual2.vhd" "ram\[0\]~60" { Text "F:/liangshuo程序/1/fen_zu_interlacing/RAM_MN_dual2.vhd" 27 -1 0 } }  } 0 0 "Inferred altsyncram megafunction (NUMWORDS_A=%2!d!, WIDTH_A=%3!d!) from the following design logic: \"%1!s!\"" 0 0} { "Info" "IOPT_ALTSYNCRAM_INFERRED" "jieinterlace:inst2\|RAM_MN_dual:inst5\|ram\[0\]~60 32 2 " "Info: Inferred altsyncram megafunction (NUMWORDS_A=32, WIDTH_A=2) from the following design logic: \"jieinterlace:inst2\|RAM_MN_dual:inst5\|ram\[0\]~60\"" {  } { { "RAM_MN_dual.vhd" "ram\[0\]~60" { Text "F:/liangshuo程序/1/fen_zu_interlacing/RAM_MN_dual.vhd" 27 -1 0 } }  } 0 0 "Inferred altsyncram megafunction (NUMWORDS_A=%2!d!, WIDTH_A=%3!d!) from the following design logic: \"%1!s!\"" 0 0}  } {  } 0 0 "Inferred %1!d! megafunctions from design logic" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/program files/altera/quartus60/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus60/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "d:/program files/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 426 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "jieinterlace:inst2\|RAM_MN_dual2:inst6\|altsyncram:ram_rtl_0 " "Info: Elaborated megafunction instantiation \"jieinterlace:inst2\|RAM_MN_dual2:inst6\|altsyncram:ram_rtl_0\"" {  } {  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_tmi1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_tmi1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_tmi1 " "Info: Found entity 1: altsyncram_tmi1" {  } { { "db/altsyncram_tmi1.tdf" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/db/altsyncram_tmi1.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "57 " "Info: Implemented 57 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "6 " "Info: Implemented 6 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "46 " "Info: Implemented 46 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0} { "Info" "ISCL_SCL_TM_RAMS" "4 " "Info: Implemented 4 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 23 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 23 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 08 21:18:58 2008 " "Info: Processing ended: Tue Apr 08 21:18:58 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}