jieinterlace.map.qmsg

来自「一个简单的交织实现程序」· QMSG 代码 · 共 50 行 · 第 1/3 页

{ "Warning" "WSGN_SEARCH_FILE" "RAM_MN_dual.vhd 2 1 " "Warning: Using design file RAM_MN_dual.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 RAM_MN_dual-beha " "Info: Found design unit 1: RAM_MN_dual-beha" {  } { { "RAM_MN_dual.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/RAM_MN_dual.vhd" 19 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 RAM_MN_dual " "Info: Found entity 1: RAM_MN_dual" {  } { { "RAM_MN_dual.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/RAM_MN_dual.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "RAM_MN_dual jieinterlace:inst2\|RAM_MN_dual:inst5 " "Info: Elaborating entity \"RAM_MN_dual\" for hierarchy \"jieinterlace:inst2\|RAM_MN_dual:inst5\"" {  } { { "jieinterlace.bdf" "inst5" { Schematic "F:/liangshuo程序/1/fen_zu_interlacing/jieinterlace.bdf" { { -496 504 640 -368 "inst5" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "counter.v 1 1 " "Warning: Using design file counter.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 counter " "Info: Found entity 1: counter" {  } { { "counter.v" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/counter.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter jieinterlace:inst2\|counter:inst8 " "Info: Elaborating entity \"counter\" for hierarchy \"jieinterlace:inst2\|counter:inst8\"" {  } { { "jieinterlace.bdf" "inst8" { Schematic "F:/liangshuo程序/1/fen_zu_interlacing/jieinterlace.bdf" { { -384 -104 48 -288 "inst8" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "rom_mn_interlace.vhd 2 1 " "Warning: Using design file rom_mn_interlace.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 rom_mn_interlace-beha " "Info: Found design unit 1: rom_mn_interlace-beha" {  } { { "rom_mn_interlace.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/rom_mn_interlace.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 rom_mn_interlace " "Info: Found entity 1: rom_mn_interlace" {  } { { "rom_mn_interlace.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/rom_mn_interlace.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom_mn_interlace jieinterlace:inst2\|rom_mn_interlace:inst " "Info: Elaborating entity \"rom_mn_interlace\" for hierarchy \"jieinterlace:inst2\|rom_mn_interlace:inst\"" {  } { { "jieinterlace.bdf" "inst" { Schematic "F:/liangshuo程序/1/fen_zu_interlacing/jieinterlace.bdf" { { -480 200 408 -384 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "rom_mn_seq.vhd 2 1 " "Warning: Using design file rom_mn_seq.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 rom_mn_seq-beha " "Info: Found design unit 1: rom_mn_seq-beha" {  } { { "rom_mn_seq.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/rom_mn_seq.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 rom_mn_seq " "Info: Found entity 1: rom_mn_seq" {  } { { "rom_mn_seq.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/rom_mn_seq.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom_mn_seq jieinterlace:inst2\|rom_mn_seq:inst9 " "Info: Elaborating entity \"rom_mn_seq\" for hierarchy \"jieinterlace:inst2\|rom_mn_seq:inst9\"" {  } { { "jieinterlace.bdf" "inst9" { Schematic "F:/liangshuo程序/1/fen_zu_interlacing/jieinterlace.bdf" { { -344 216 400 -248 "inst9" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "RAM_MN_dual2.vhd 2 1 " "Warning: Using design file RAM_MN_dual2.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 RAM_MN_dual2-beha " "Info: Found design unit 1: RAM_MN_dual2-beha" {  } { { "RAM_MN_dual2.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/RAM_MN_dual2.vhd" 19 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 RAM_MN_dual2 " "Info: Found entity 1: RAM_MN_dual2" {  } { { "RAM_MN_dual2.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/RAM_MN_dual2.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "RAM_MN_dual2 jieinterlace:inst2\|RAM_MN_dual2:inst6 " "Info: Elaborating entity \"RAM_MN_dual2\" for hierarchy \"jieinterlace:inst2\|RAM_MN_dual2:inst6\"" {  } { { "jieinterlace.bdf" "inst6" { Schematic "F:/liangshuo程序/1/fen_zu_interlacing/jieinterlace.bdf" { { -344 520 656 -216 "inst6" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "cobination.v 1 1 " "Warning: Using design file cobination.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 cobination " "Info: Found entity 1: cobination" {  } { { "cobination.v" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/cobination.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cobination jieinterlace:inst2\|cobination:inst12 " "Info: Elaborating entity \"cobination\" for hierarchy \"jieinterlace:inst2\|cobination:inst12\"" {  } { { "jieinterlace.bdf" "inst12" { Schematic "F:/liangshuo程序/1/fen_zu_interlacing/jieinterlace.bdf" { { -424 712 808 -328 "inst12" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "interlace.bdf 1 1 " "Warning: Using design file interlace.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 interlace " "Info: Found entity 1: interlace" {  } { { "interlace.bdf" "" { Schematic "F:/liangshuo程序/1/fen_zu_interlacing/interlace.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "interlace interlace:inst " "Info: Elaborating entity \"interlace\" for hierarchy \"interlace:inst\"" {  } { { "jiaozhijiejiaozhi.bdf" "inst" { Schematic "F:/liangshuo程序/1/fen_zu_interlacing/jiaozhijiejiaozhi.bdf" { { 80 232 368 272 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WGDFX_INCONSISTENT_BASE_NAME" "" "Warning: Found multiple base names" {  } { { "interlace.bdf" "" { Schematic "F:/liangshuo程序/1/fen_zu_interlacing/interlace.bdf" { { -504 120 296 -488 "cnt\[4..0\]" "" } { -504 120 296 -488 "cnt\[4..0\]" "" } { -504 120 296 -488 "cnt\[4..0\]" "" } { -504 120 296 -488 "cnt\[4..0\]" "" } { -504 120 296 -488 "cnt\[4..0\]" "" } { -504 120 296 -488 "cnt\[4..0\]" "" } } } }  } 0 0 "Found multiple base names" 0 0}
{ "Warning" "WGDFX_INCONSISTENT_BASE_NAME" "" "Warning: Found multiple base names" {  } { { "interlace.bdf" "" { Schematic "F:/liangshuo程序/1/fen_zu_interlacing/interlace.bdf" { { -544 440 616 -528 "cnt1\[4..0\]" "" } { -544 440 616 -528 "cnt1\[4..0\]" "" } { -544 440 616 -528 "cnt1\[4..0\]" "" } { -544 440 616 -528 "cnt1\[4..0\]" "" } { -544 440 616 -528 "cnt1\[4..0\]" "" } { -544 440 616 -528 "cnt1\[4..0\]" "" } } } }  } 0 0 "Found multiple base names" 0 0}
{ "Warning" "WGDFX_INCONSISTENT_BASE_NAME" "" "Warning: Found multiple base names" {  } { { "interlace.bdf" "" { Schematic "F:/liangshuo程序/1/fen_zu_interlacing/interlace.bdf" { { -528 456 632 -512 "cnt2\[4..0\]" "" } { -528 456 632 -512 "cnt2\[4..0\]" "" } { -528 456 632 -512 "cnt2\[4..0\]" "" } { -528 456 632 -512 "cnt2\[4..0\]" "" } { -528 456 632 -512 "cnt2\[4..0\]" "" } { -528 456 632 -512 "cnt2\[4..0\]" "" } } } }  } 0 0 "Found multiple base names" 0 0}