jieinterlace.hif

一个简单的交织实现程序

Version 6.0 Build 178 04/27/2006 SJ Full Version
7
530
OFF
OFF
OFF
OFF
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
jieinterlace
# storage
db|jieinterlace.(1).cnf
db|jieinterlace.(1).cnf
# case_insensitive
# source_file
jieinterlace.bdf
5f22aeff288c6c1a653b46d90509a2b
24
# hierarchies {
jieinterlace:inst2
}
# end
# entity
RAM_MN_dual
# storage
db|jieinterlace.(2).cnf
db|jieinterlace.(2).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
RAM_MN_dual.vhd
e871b0e6b6b145189bdf51b4d715b623
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
jieinterlace:inst2|RAM_MN_dual:inst5
interlace:inst|RAM_MN_dual:inst5
}
# end
# entity
counter
# storage
db|jieinterlace.(3).cnf
db|jieinterlace.(3).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
counter.v
b2dc6417d174338513edf5ec590ac5
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
NN
30
PARAMETER_DEC
DEF
}
# hierarchies {
jieinterlace:inst2|counter:inst8
interlace:inst|counter:inst8
}
# end
# entity
rom_mn_interlace
# storage
db|jieinterlace.(4).cnf
db|jieinterlace.(4).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
rom_mn_interlace.vhd
5aa1212144aa74528dee3ebeb6d9d70
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
jieinterlace:inst2|rom_mn_interlace:inst
interlace:inst|rom_mn_interlace:inst
}
# end
# entity
rom_mn_seq
# storage
db|jieinterlace.(5).cnf
db|jieinterlace.(5).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
rom_mn_seq.vhd
20f9cc628de20e6373bdb20872785ae
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
jieinterlace:inst2|rom_mn_seq:inst9
interlace:inst|rom_mn_seq:inst9
}
# end
# entity
RAM_MN_dual2
# storage
db|jieinterlace.(6).cnf
db|jieinterlace.(6).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
RAM_MN_dual2.vhd
46a32f26339c494bf0fbedff7acf51c
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
jieinterlace:inst2|RAM_MN_dual2:inst6
interlace:inst|RAM_MN_dual2:inst6
}
# end
# entity
cobination
# storage
db|jieinterlace.(7).cnf
db|jieinterlace.(7).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
cobination.v
98ed84fa66b4674a16eb68f9ebaaf299
7
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
jieinterlace:inst2|cobination:inst12
interlace:inst|cobination:inst12
}
# end
# entity
interlace
# storage
db|jieinterlace.(8).cnf
db|jieinterlace.(8).cnf
# case_insensitive
# source_file
interlace.bdf
8cfc9599b066f5452552dbcd2207241
24
# hierarchies {
interlace:inst
}
# end
# entity
source
# storage
db|jieinterlace.(9).cnf
db|jieinterlace.(9).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
source.vhd
894f4b6cb81ced53fd16ed47e62e31e8
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
interlace:inst|source:inst1
}
# end
# entity
altsyncram
# storage
db|jieinterlace.(10).cnf
db|jieinterlace.(10).cnf
# case_insensitive
# source_file
d:|program files|altera|quartus60|libraries|megafunctions|altsyncram.tdf
c9a54fc8e33741c15b27e3d74d615aff
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
2
PARAMETER_UNKNOWN
USR
WIDTHAD_A
5
PARAMETER_UNKNOWN
USR
NUMWORDS_A
32
PARAMETER_UNKNOWN
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
2
PARAMETER_UNKNOWN
USR
WIDTHAD_B
5
PARAMETER_UNKNOWN
USR
NUMWORDS_B
32
PARAMETER_UNKNOWN
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
OLD_DATA
PARAMETER_UNKNOWN
USR
INIT_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Stratix II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_tmi1
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
q_b1
-1
3
q_b0
-1
3
data_a1
-1
3
data_a0
-1
3
clock0
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# include_file {
d:|program files|altera|quartus60|libraries|megafunctions|stratix_ram_block.inc
2263a3bdfffeb150af977ee13902f70
d:|program files|altera|quartus60|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
d:|program files|altera|quartus60|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
d:|program files|altera|quartus60|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
d:|program files|altera|quartus60|libraries|megafunctions|altsyncram.inc
2d485e3cf75d4048974bdbf0d920cb89
d:|program files|altera|quartus60|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
d:|program files|altera|quartus60|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
d:|program files|altera|quartus60|libraries|megafunctions|altram.inc
e66a83eccf6717bed97c99d891ad085
d:|program files|altera|quartus60|libraries|megafunctions|altdpram.inc
4e1931f9814db9f22f22b9eb377c65d6
d:|program files|altera|quartus60|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
}
# end
# entity
altsyncram_tmi1
# storage
db|jieinterlace.(11).cnf
db|jieinterlace.(11).cnf
# case_insensitive
# source_file
db|altsyncram_tmi1.tdf
36be307cafc349d74e252d157e90cd15
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_a
-1
3
q_b1
-1
3
q_b0
-1
3
data_a1
-1
3
data_a0
-1
3
clock0
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
none
0
}
# end
# entity
jiaozhijiejiaozhi
# storage
db|jieinterlace.(0).cnf
db|jieinterlace.(0).cnf
# case_insensitive
# source_file
jiaozhijiejiaozhi.bdf
70448cf37e1b60bc656e4878b622c6
24
# hierarchies {
|
}
# end
# complete