interlace.map.qmsg

一个简单的交织实现程序

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom_mn_interlace rom_mn_interlace:inst " "Info: Elaborating entity \"rom_mn_interlace\" for hierarchy \"rom_mn_interlace:inst\"" {  } { { "interlace.bdf" "inst" { Schematic "F:/111/fen_zu_interlacing/interlace.bdf" { { -480 200 408 -384 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rom_mn_seq rom_mn_seq:inst9 " "Info: Elaborating entity \"rom_mn_seq\" for hierarchy \"rom_mn_seq:inst9\"" {  } { { "interlace.bdf" "inst9" { Schematic "F:/111/fen_zu_interlacing/interlace.bdf" { { -344 216 400 -248 "inst9" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "RAM_MN_dual2 RAM_MN_dual2:inst6 " "Info: Elaborating entity \"RAM_MN_dual2\" for hierarchy \"RAM_MN_dual2:inst6\"" {  } { { "interlace.bdf" "inst6" { Schematic "F:/111/fen_zu_interlacing/interlace.bdf" { { -344 520 656 -216 "inst6" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "cobination.v 1 1 " "Warning: Using design file cobination.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 cobination " "Info: Found entity 1: cobination" {  } { { "cobination.v" "" { Text "F:/111/fen_zu_interlacing/cobination.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cobination cobination:inst12 " "Info: Elaborating entity \"cobination\" for hierarchy \"cobination:inst12\"" {  } { { "interlace.bdf" "inst12" { Schematic "F:/111/fen_zu_interlacing/interlace.bdf" { { -424 712 808 -328 "inst12" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "rom_mn_interlace:inst\|interlace_addr\[0\] rom_mn_seq:inst9\|seq_addr\[0\] " "Info: Duplicate register \"rom_mn_interlace:inst\|interlace_addr\[0\]\" merged to single register \"rom_mn_seq:inst9\|seq_addr\[0\]\"" {  } { { "rom_mn_interlace.vhd" "" { Text "F:/111/fen_zu_interlacing/rom_mn_interlace.vhd" 62 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Warning" "WOPT_RAM_PASS_THROUGH_LOGIC_INSERTED_ALTSYNCRAM" "RAM_MN_dual:inst5\|ram\[0\]~60 " "Warning: Created node \"RAM_MN_dual:inst5\|ram\[0\]~60\" as a RAM by generating altsyncram megafunction to implement register logic with M512 or M4K memory block or M-RAM. Pass-through logic has been added." {  } { { "RAM_MN_dual.vhd" "ram\[0\]~60" { Text "F:/111/fen_zu_interlacing/RAM_MN_dual.vhd" 27 -1 0 } }  } 0 0 "Created node \"%1!s!\" as a RAM by generating altsyncram megafunction to implement register logic with M512 or M4K memory block or M-RAM. Pass-through logic has been added." 0 0}
{ "Warning" "WOPT_RAM_PASS_THROUGH_LOGIC_INSERTED_ALTSYNCRAM" "RAM_MN_dual2:inst6\|ram\[0\]~60 " "Warning: Created node \"RAM_MN_dual2:inst6\|ram\[0\]~60\" as a RAM by generating altsyncram megafunction to implement register logic with M512 or M4K memory block or M-RAM. Pass-through logic has been added." {  } { { "RAM_MN_dual2.vhd" "ram\[0\]~60" { Text "F:/111/fen_zu_interlacing/RAM_MN_dual2.vhd" 27 -1 0 } }  } 0 0 "Created node \"%1!s!\" as a RAM by generating altsyncram megafunction to implement register logic with M512 or M4K memory block or M-RAM. Pass-through logic has been added." 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "RAM_MN_dual:inst5\|Mux0~60 rom_mn_interlace:inst\|interlace_addr\[4\] " "Info: Duplicate register \"RAM_MN_dual:inst5\|Mux0~60\" merged to single register \"rom_mn_interlace:inst\|interlace_addr\[4\]\"" {  } { { "RAM_MN_dual.vhd" "" { Text "F:/111/fen_zu_interlacing/RAM_MN_dual.vhd" 32 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "RAM_MN_dual2:inst6\|Mux0~60 rom_mn_interlace:inst\|interlace_addr\[4\] " "Info: Duplicate register \"RAM_MN_dual2:inst6\|Mux0~60\" merged to single register \"rom_mn_interlace:inst\|interlace_addr\[4\]\"" {  } { { "RAM_MN_dual2.vhd" "" { Text "F:/111/fen_zu_interlacing/RAM_MN_dual2.vhd" 32 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "RAM_MN_dual:inst5\|Mux0~57 rom_mn_interlace:inst\|interlace_addr\[3\] " "Info: Duplicate register \"RAM_MN_dual:inst5\|Mux0~57\" merged to single register \"rom_mn_interlace:inst\|interlace_addr\[3\]\"" {  } { { "RAM_MN_dual.vhd" "" { Text "F:/111/fen_zu_interlacing/RAM_MN_dual.vhd" 32 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "RAM_MN_dual2:inst6\|Mux0~57 rom_mn_interlace:inst\|interlace_addr\[3\] " "Info: Duplicate register \"RAM_MN_dual2:inst6\|Mux0~57\" merged to single register \"rom_mn_interlace:inst\|interlace_addr\[3\]\"" {  } { { "RAM_MN_dual2.vhd" "" { Text "F:/111/fen_zu_interlacing/RAM_MN_dual2.vhd" 32 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "RAM_MN_dual:inst5\|Mux0~54 rom_mn_interlace:inst\|interlace_addr\[2\] " "Info: Duplicate register \"RAM_MN_dual:inst5\|Mux0~54\" merged to single register \"rom_mn_interlace:inst\|interlace_addr\[2\]\"" {  } { { "RAM_MN_dual.vhd" "" { Text "F:/111/fen_zu_interlacing/RAM_MN_dual.vhd" 32 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "RAM_MN_dual2:inst6\|Mux0~54 rom_mn_interlace:inst\|interlace_addr\[2\] " "Info: Duplicate register \"RAM_MN_dual2:inst6\|Mux0~54\" merged to single register \"rom_mn_interlace:inst\|interlace_addr\[2\]\"" {  } { { "RAM_MN_dual2.vhd" "" { Text "F:/111/fen_zu_interlacing/RAM_MN_dual2.vhd" 32 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "RAM_MN_dual:inst5\|Mux0~51 rom_mn_interlace:inst\|interlace_addr\[1\] " "Info: Duplicate register \"RAM_MN_dual:inst5\|Mux0~51\" merged to single register \"rom_mn_interlace:inst\|interlace_addr\[1\]\"" {  } { { "RAM_MN_dual.vhd" "" { Text "F:/111/fen_zu_interlacing/RAM_MN_dual.vhd" 32 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "RAM_MN_dual2:inst6\|Mux0~51 rom_mn_interlace:inst\|interlace_addr\[1\] " "Info: Duplicate register \"RAM_MN_dual2:inst6\|Mux0~51\" merged to single register \"rom_mn_interlace:inst\|interlace_addr\[1\]\"" {  } { { "RAM_MN_dual2.vhd" "" { Text "F:/111/fen_zu_interlacing/RAM_MN_dual2.vhd" 32 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "RAM_MN_dual:inst5\|Mux0~48 rom_mn_seq:inst9\|seq_addr\[0\] " "Info: Duplicate register \"RAM_MN_dual:inst5\|Mux0~48\" merged to single register \"rom_mn_seq:inst9\|seq_addr\[0\]\"" {  } { { "RAM_MN_dual.vhd" "" { Text "F:/111/fen_zu_interlacing/RAM_MN_dual.vhd" 32 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "RAM_MN_dual2:inst6\|Mux0~48 rom_mn_seq:inst9\|seq_addr\[0\] " "Info: Duplicate register \"RAM_MN_dual2:inst6\|Mux0~48\" merged to single register \"rom_mn_seq:inst9\|seq_addr\[0\]\"" {  } { { "RAM_MN_dual2.vhd" "" { Text "F:/111/fen_zu_interlacing/RAM_MN_dual2.vhd" 32 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "RAM_MN_dual2:inst6\|Mux0~62 RAM_MN_dual:inst5\|Mux0~62 " "Info: Duplicate register \"RAM_MN_dual2:inst6\|Mux0~62\" merged to single register \"RAM_MN_dual:inst5\|Mux0~62\"" {  } { { "RAM_MN_dual2.vhd" "" { Text "F:/111/fen_zu_interlacing/RAM_MN_dual2.vhd" 32 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "RAM_MN_dual2:inst6\|Mux0~47 RAM_MN_dual:inst5\|Mux0~47 " "Info: Duplicate register \"RAM_MN_dual2:inst6\|Mux0~47\" merged to single register \"RAM_MN_dual:inst5\|Mux0~47\"" {  } { { "RAM_MN_dual2.vhd" "" { Text "F:/111/fen_zu_interlacing/RAM_MN_dual2.vhd" 32 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "RAM_MN_dual2:inst6\|Mux0~50 RAM_MN_dual:inst5\|Mux0~50 " "Info: Duplicate register \"RAM_MN_dual2:inst6\|Mux0~50\" merged to single register \"RAM_MN_dual:inst5\|Mux0~50\"" {  } { { "RAM_MN_dual2.vhd" "" { Text "F:/111/fen_zu_interlacing/RAM_MN_dual2.vhd" 32 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "RAM_MN_dual2:inst6\|Mux0~53 RAM_MN_dual:inst5\|Mux0~53 " "Info: Duplicate register \"RAM_MN_dual2:inst6\|Mux0~53\" merged to single register \"RAM_MN_dual:inst5\|Mux0~53\"" {  } { { "RAM_MN_dual2.vhd" "" { Text "F:/111/fen_zu_interlacing/RAM_MN_dual2.vhd" 32 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "RAM_MN_dual2:inst6\|Mux0~56 RAM_MN_dual:inst5\|Mux0~56 " "Info: Duplicate register \"RAM_MN_dual2:inst6\|Mux0~56\" merged to single register \"RAM_MN_dual:inst5\|Mux0~56\"" {  } { { "RAM_MN_dual2.vhd" "" { Text "F:/111/fen_zu_interlacing/RAM_MN_dual2.vhd" 32 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "RAM_MN_dual2:inst6\|Mux0~59 RAM_MN_dual:inst5\|Mux0~59 " "Info: Duplicate register \"RAM_MN_dual2:inst6\|Mux0~59\" merged to single register \"RAM_MN_dual:inst5\|Mux0~59\"" {  } { { "RAM_MN_dual2.vhd" "" { Text "F:/111/fen_zu_interlacing/RAM_MN_dual2.vhd" 32 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "rom_mn_seq:inst9\|seq_addr\[0\] counter:inst8\|series_addr\[0\] " "Info: Duplicate register \"rom_mn_seq:inst9\|seq_addr\[0\]\" merged to single register \"counter:inst8\|series_addr\[0\]\", power-up level changed" {  } { { "rom_mn_seq.vhd" "" { Text "F:/111/fen_zu_interlacing/rom_mn_seq.vhd" 54 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\", power-up level changed" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "counter:inst8\|cnt\[0\] counter:inst8\|series_addr\[0\] " "Info: Duplicate register \"counter:inst8\|cnt\[0\]\" merged to single register \"counter:inst8\|series_addr\[0\]\", power-up level changed" {  } { { "counter.v" "" { Text "F:/111/fen_zu_interlacing/counter.v" 15 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\", power-up level changed" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "source:inst1\|m\[0\] RAM_MN_dual:inst5\|Mux0~47 " "Info: Duplicate register \"source:inst1\|m\[0\]\" merged to single register \"RAM_MN_dual:inst5\|Mux0~47\"" {  } { { "source/source.vhd" "" { Text "F:/111/fen_zu_interlacing/source/source.vhd" 20 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "2 " "Info: Inferred 2 megafunctions from design logic" { { "Info" "IOPT_ALTSYNCRAM_INFERRED" "RAM_MN_dual:inst5\|ram\[0\]~60 32 1 " "Info: Inferred altsyncram megafunction (NUMWORDS_A=32, WIDTH_A=1) from the following design logic: \"RAM_MN_dual:inst5\|ram\[0\]~60\"" {  } { { "RAM_MN_dual.vhd" "ram\[0\]~60" { Text "F:/111/fen_zu_interlacing/RAM_MN_dual.vhd" 27 -1 0 } }  } 0 0 "Inferred altsyncram megafunction (NUMWORDS_A=%2!d!, WIDTH_A=%3!d!) from the following design logic: \"%1!s!\"" 0 0} { "Info" "IOPT_ALTSYNCRAM_INFERRED" "RAM_MN_dual2:inst6\|ram\[0\]~60 32 1 " "Info: Inferred altsyncram megafunction (NUMWORDS_A=32, WIDTH_A=1) from the following design logic: \"RAM_MN_dual2:inst6\|ram\[0\]~60\"" {  } { { "RAM_MN_dual2.vhd" "ram\[0\]~60" { Text "F:/111/fen_zu_interlacing/RAM_MN_dual2.vhd" 27 -1 0 } }  } 0 0 "Inferred altsyncram megafunction (NUMWORDS_A=%2!d!, WIDTH_A=%3!d!) from the following design logic: \"%1!s!\"" 0 0}  } {  } 0 0 "Inferred %1!d! megafunctions from design logic" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/program files/altera/quartus60/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus60/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "d:/program files/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 426 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "RAM_MN_dual:inst5\|altsyncram:ram_rtl_0 " "Info: Elaborated megafunction instantiation \"RAM_MN_dual:inst5\|altsyncram:ram_rtl_0\"" {  } {  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_rmi1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_rmi1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_rmi1 " "Info: Found entity 1: altsyncram_rmi1" {  } { { "db/altsyncram_rmi1.tdf" "" { Text "F:/111/fen_zu_interlacing/db/altsyncram_rmi1.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "67 " "Info: Implemented 67 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "20 " "Info: Implemented 20 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "44 " "Info: Implemented 44 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0} { "Info" "ISCL_SCL_TM_RAMS" "2 " "Info: Implemented 2 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 6 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 07 22:22:09 2008 " "Info: Processing ended: Mon Apr 07 22:22:09 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}