interlace.map.qmsg

一个简单的交织实现程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Apr 07 22:22:06 2008 " "Info: Processing started: Mon Apr 07 22:22:06 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off interlace -c interlace " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off interlace -c interlace" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "counter.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file counter.v" { { "Info" "ISGN_ENTITY_NAME" "1 counter " "Info: Found entity 1: counter" {  } { { "counter.v" "" { Text "F:/111/fen_zu_interlacing/counter.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom_mn_seq.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file rom_mn_seq.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 rom_mn_seq-beha " "Info: Found design unit 1: rom_mn_seq-beha" {  } { { "rom_mn_seq.vhd" "" { Text "F:/111/fen_zu_interlacing/rom_mn_seq.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 rom_mn_seq " "Info: Found entity 1: rom_mn_seq" {  } { { "rom_mn_seq.vhd" "" { Text "F:/111/fen_zu_interlacing/rom_mn_seq.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rom_mn_interlace.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file rom_mn_interlace.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 rom_mn_interlace-beha " "Info: Found design unit 1: rom_mn_interlace-beha" {  } { { "rom_mn_interlace.vhd" "" { Text "F:/111/fen_zu_interlacing/rom_mn_interlace.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 rom_mn_interlace " "Info: Found entity 1: rom_mn_interlace" {  } { { "rom_mn_interlace.vhd" "" { Text "F:/111/fen_zu_interlacing/rom_mn_interlace.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "interlace.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file interlace.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 interlace " "Info: Found entity 1: interlace" {  } { { "interlace.bdf" "" { Schematic "F:/111/fen_zu_interlacing/interlace.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "RAM_MN_dual.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file RAM_MN_dual.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 RAM_MN_dual-beha " "Info: Found design unit 1: RAM_MN_dual-beha" {  } { { "RAM_MN_dual.vhd" "" { Text "F:/111/fen_zu_interlacing/RAM_MN_dual.vhd" 19 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 RAM_MN_dual " "Info: Found entity 1: RAM_MN_dual" {  } { { "RAM_MN_dual.vhd" "" { Text "F:/111/fen_zu_interlacing/RAM_MN_dual.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "RAM_MN_dual2.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file RAM_MN_dual2.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 RAM_MN_dual2-beha " "Info: Found design unit 1: RAM_MN_dual2-beha" {  } { { "RAM_MN_dual2.vhd" "" { Text "F:/111/fen_zu_interlacing/RAM_MN_dual2.vhd" 19 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 RAM_MN_dual2 " "Info: Found entity 1: RAM_MN_dual2" {  } { { "RAM_MN_dual2.vhd" "" { Text "F:/111/fen_zu_interlacing/RAM_MN_dual2.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "source/source.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file source/source.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 source-a " "Info: Found design unit 1: source-a" {  } { { "source/source.vhd" "" { Text "F:/111/fen_zu_interlacing/source/source.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 source " "Info: Found entity 1: source" {  } { { "source/source.vhd" "" { Text "F:/111/fen_zu_interlacing/source/source.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "interlace " "Info: Elaborating entity \"interlace\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WGDFX_INCONSISTENT_BASE_NAME" "" "Warning: Found multiple base names" {  } { { "interlace.bdf" "" { Schematic "F:/111/fen_zu_interlacing/interlace.bdf" { { -504 120 296 -488 "cnt\[4..0\]" "" } { -504 120 296 -488 "cnt\[4..0\]" "" } { -504 120 296 -488 "cnt\[4..0\]" "" } { -504 120 296 -488 "cnt\[4..0\]" "" } { -504 120 296 -488 "cnt\[4..0\]" "" } { -504 120 296 -488 "cnt\[4..0\]" "" } } } }  } 0 0 "Found multiple base names" 0 0}
{ "Warning" "WGDFX_INCONSISTENT_BASE_NAME" "" "Warning: Found multiple base names" {  } { { "interlace.bdf" "" { Schematic "F:/111/fen_zu_interlacing/interlace.bdf" { { -544 440 616 -528 "cnt1\[4..0\]" "" } { -544 440 616 -528 "cnt1\[4..0\]" "" } { -544 440 616 -528 "cnt1\[4..0\]" "" } { -544 440 616 -528 "cnt1\[4..0\]" "" } { -544 440 616 -528 "cnt1\[4..0\]" "" } { -544 440 616 -528 "cnt1\[4..0\]" "" } } } }  } 0 0 "Found multiple base names" 0 0}
{ "Warning" "WGDFX_INCONSISTENT_BASE_NAME" "" "Warning: Found multiple base names" {  } { { "interlace.bdf" "" { Schematic "F:/111/fen_zu_interlacing/interlace.bdf" { { -528 456 632 -512 "cnt2\[4..0\]" "" } { -528 456 632 -512 "cnt2\[4..0\]" "" } { -528 456 632 -512 "cnt2\[4..0\]" "" } { -528 456 632 -512 "cnt2\[4..0\]" "" } { -528 456 632 -512 "cnt2\[4..0\]" "" } { -528 456 632 -512 "cnt2\[4..0\]" "" } } } }  } 0 0 "Found multiple base names" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "RAM_MN_dual RAM_MN_dual:inst5 " "Info: Elaborating entity \"RAM_MN_dual\" for hierarchy \"RAM_MN_dual:inst5\"" {  } { { "interlace.bdf" "inst5" { Schematic "F:/111/fen_zu_interlacing/interlace.bdf" { { -496 504 640 -368 "inst5" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter counter:inst8 " "Info: Elaborating entity \"counter\" for hierarchy \"counter:inst8\"" {  } { { "interlace.bdf" "inst8" { Schematic "F:/111/fen_zu_interlacing/interlace.bdf" { { -384 -104 48 -288 "inst8" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "source source:inst1 " "Info: Elaborating entity \"source\" for hierarchy \"source:inst1\"" {  } { { "interlace.bdf" "inst1" { Schematic "F:/111/fen_zu_interlacing/interlace.bdf" { { -144 144 240 -48 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}