interlace.map.rpt
来自「一个简单的交织实现程序」· RPT 代码 · 共 473 行 · 第 1/3 页
RPT
473 行
; RDCONTROL_ACLR_B ; NONE ; Untyped ;
; BYTEENA_ACLR_B ; NONE ; Untyped ;
; WIDTH_BYTEENA_A ; 1 ; Untyped ;
; WIDTH_BYTEENA_B ; 1 ; Untyped ;
; RAM_BLOCK_TYPE ; AUTO ; Untyped ;
; BYTE_SIZE ; 8 ; Untyped ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA ; Untyped ;
; INIT_FILE ; UNUSED ; Untyped ;
; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
; MAXIMUM_DEPTH ; 0 ; Untyped ;
; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
; DEVICE_FAMILY ; Stratix II ; Untyped ;
; CBXI_PARAMETER ; altsyncram_rmi1 ; Untyped ;
+------------------------------------+-----------------+----------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: RAM_MN_dual2:inst6|altsyncram:ram_rtl_1 ;
+------------------------------------+-----------------+-----------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------------------+-----------------+-----------------------------------+
; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; OPERATION_MODE ; DUAL_PORT ; Untyped ;
; WIDTH_A ; 1 ; Untyped ;
; WIDTHAD_A ; 5 ; Untyped ;
; NUMWORDS_A ; 32 ; Untyped ;
; OUTDATA_REG_A ; UNREGISTERED ; Untyped ;
; ADDRESS_ACLR_A ; NONE ; Untyped ;
; OUTDATA_ACLR_A ; NONE ; Untyped ;
; WRCONTROL_ACLR_A ; NONE ; Untyped ;
; INDATA_ACLR_A ; NONE ; Untyped ;
; BYTEENA_ACLR_A ; NONE ; Untyped ;
; WIDTH_B ; 1 ; Untyped ;
; WIDTHAD_B ; 5 ; Untyped ;
; NUMWORDS_B ; 32 ; Untyped ;
; INDATA_REG_B ; CLOCK1 ; Untyped ;
; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
; ADDRESS_REG_B ; CLOCK0 ; Untyped ;
; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
; INDATA_ACLR_B ; NONE ; Untyped ;
; WRCONTROL_ACLR_B ; NONE ; Untyped ;
; ADDRESS_ACLR_B ; NONE ; Untyped ;
; OUTDATA_ACLR_B ; NONE ; Untyped ;
; RDCONTROL_ACLR_B ; NONE ; Untyped ;
; BYTEENA_ACLR_B ; NONE ; Untyped ;
; WIDTH_BYTEENA_A ; 1 ; Untyped ;
; WIDTH_BYTEENA_B ; 1 ; Untyped ;
; RAM_BLOCK_TYPE ; AUTO ; Untyped ;
; BYTE_SIZE ; 8 ; Untyped ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA ; Untyped ;
; INIT_FILE ; UNUSED ; Untyped ;
; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
; MAXIMUM_DEPTH ; 0 ; Untyped ;
; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
; DEVICE_FAMILY ; Stratix II ; Untyped ;
; CBXI_PARAMETER ; altsyncram_rmi1 ; Untyped ;
+------------------------------------+-----------------+-----------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Mon Apr 07 22:22:06 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off interlace -c interlace
Info: Found 1 design units, including 1 entities, in source file counter.v
Info: Found entity 1: counter
Info: Found 2 design units, including 1 entities, in source file rom_mn_seq.vhd
Info: Found design unit 1: rom_mn_seq-beha
Info: Found entity 1: rom_mn_seq
Info: Found 2 design units, including 1 entities, in source file rom_mn_interlace.vhd
Info: Found design unit 1: rom_mn_interlace-beha
Info: Found entity 1: rom_mn_interlace
Info: Found 1 design units, including 1 entities, in source file interlace.bdf
Info: Found entity 1: interlace
Info: Found 2 design units, including 1 entities, in source file RAM_MN_dual.vhd
Info: Found design unit 1: RAM_MN_dual-beha
Info: Found entity 1: RAM_MN_dual
Info: Found 2 design units, including 1 entities, in source file RAM_MN_dual2.vhd
Info: Found design unit 1: RAM_MN_dual2-beha
Info: Found entity 1: RAM_MN_dual2
Info: Found 2 design units, including 1 entities, in source file source/source.vhd
Info: Found design unit 1: source-a
Info: Found entity 1: source
Info: Elaborating entity "interlace" for the top level hierarchy
Warning: Found multiple base names
Warning: Found multiple base names
Warning: Found multiple base names
Info: Elaborating entity "RAM_MN_dual" for hierarchy "RAM_MN_dual:inst5"
Info: Elaborating entity "counter" for hierarchy "counter:inst8"
Info: Elaborating entity "source" for hierarchy "source:inst1"
Info: Elaborating entity "rom_mn_interlace" for hierarchy "rom_mn_interlace:inst"
Info: Elaborating entity "rom_mn_seq" for hierarchy "rom_mn_seq:inst9"
Info: Elaborating entity "RAM_MN_dual2" for hierarchy "RAM_MN_dual2:inst6"
Warning: Using design file cobination.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info: Found entity 1: cobination
Info: Elaborating entity "cobination" for hierarchy "cobination:inst12"
Info: Duplicate registers merged to single register
Info: Duplicate register "rom_mn_interlace:inst|interlace_addr[0]" merged to single register "rom_mn_seq:inst9|seq_addr[0]"
Warning: Created node "RAM_MN_dual:inst5|ram[0]~60" as a RAM by generating altsyncram megafunction to implement register logic with M512 or M4K memory block or M-RAM. Pass-through logic has been added.
Warning: Created node "RAM_MN_dual2:inst6|ram[0]~60" as a RAM by generating altsyncram megafunction to implement register logic with M512 or M4K memory block or M-RAM. Pass-through logic has been added.
Info: Duplicate registers merged to single register
Info: Duplicate register "RAM_MN_dual:inst5|Mux0~60" merged to single register "rom_mn_interlace:inst|interlace_addr[4]"
Info: Duplicate register "RAM_MN_dual2:inst6|Mux0~60" merged to single register "rom_mn_interlace:inst|interlace_addr[4]"
Info: Duplicate register "RAM_MN_dual:inst5|Mux0~57" merged to single register "rom_mn_interlace:inst|interlace_addr[3]"
Info: Duplicate register "RAM_MN_dual2:inst6|Mux0~57" merged to single register "rom_mn_interlace:inst|interlace_addr[3]"
Info: Duplicate register "RAM_MN_dual:inst5|Mux0~54" merged to single register "rom_mn_interlace:inst|interlace_addr[2]"
Info: Duplicate register "RAM_MN_dual2:inst6|Mux0~54" merged to single register "rom_mn_interlace:inst|interlace_addr[2]"
Info: Duplicate register "RAM_MN_dual:inst5|Mux0~51" merged to single register "rom_mn_interlace:inst|interlace_addr[1]"
Info: Duplicate register "RAM_MN_dual2:inst6|Mux0~51" merged to single register "rom_mn_interlace:inst|interlace_addr[1]"
Info: Duplicate register "RAM_MN_dual:inst5|Mux0~48" merged to single register "rom_mn_seq:inst9|seq_addr[0]"
Info: Duplicate register "RAM_MN_dual2:inst6|Mux0~48" merged to single register "rom_mn_seq:inst9|seq_addr[0]"
Info: Duplicate register "RAM_MN_dual2:inst6|Mux0~62" merged to single register "RAM_MN_dual:inst5|Mux0~62"
Info: Duplicate register "RAM_MN_dual2:inst6|Mux0~47" merged to single register "RAM_MN_dual:inst5|Mux0~47"
Info: Duplicate register "RAM_MN_dual2:inst6|Mux0~50" merged to single register "RAM_MN_dual:inst5|Mux0~50"
Info: Duplicate register "RAM_MN_dual2:inst6|Mux0~53" merged to single register "RAM_MN_dual:inst5|Mux0~53"
Info: Duplicate register "RAM_MN_dual2:inst6|Mux0~56" merged to single register "RAM_MN_dual:inst5|Mux0~56"
Info: Duplicate register "RAM_MN_dual2:inst6|Mux0~59" merged to single register "RAM_MN_dual:inst5|Mux0~59"
Info: Duplicate registers merged to single register
Info: Duplicate register "rom_mn_seq:inst9|seq_addr[0]" merged to single register "counter:inst8|series_addr[0]", power-up level changed
Info: Duplicate register "counter:inst8|cnt[0]" merged to single register "counter:inst8|series_addr[0]", power-up level changed
Info: Duplicate register "source:inst1|m[0]" merged to single register "RAM_MN_dual:inst5|Mux0~47"
Info: Inferred 2 megafunctions from design logic
Info: Inferred altsyncram megafunction (NUMWORDS_A=32, WIDTH_A=1) from the following design logic: "RAM_MN_dual:inst5|ram[0]~60"
Info: Inferred altsyncram megafunction (NUMWORDS_A=32, WIDTH_A=1) from the following design logic: "RAM_MN_dual2:inst6|ram[0]~60"
Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus60/libraries/megafunctions/altsyncram.tdf
Info: Found entity 1: altsyncram
Info: Elaborated megafunction instantiation "RAM_MN_dual:inst5|altsyncram:ram_rtl_0"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_rmi1.tdf
Info: Found entity 1: altsyncram_rmi1
Info: Implemented 67 device resources after synthesis - the final resource count might be different
Info: Implemented 1 input pins
Info: Implemented 20 output pins
Info: Implemented 44 logic cells
Info: Implemented 2 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 6 warnings
Info: Processing ended: Mon Apr 07 22:22:09 2008
Info: Elapsed time: 00:00:03
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