jieinterlace.map.rpt

一个简单的交织实现程序

; INIT_FILE_LAYOUT                   ; PORT_A          ; Untyped                                             ;
; MAXIMUM_DEPTH                      ; 0               ; Untyped                                             ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL          ; Untyped                                             ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL          ; Untyped                                             ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL          ; Untyped                                             ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL          ; Untyped                                             ;
; DEVICE_FAMILY                      ; Stratix II      ; Untyped                                             ;
; CBXI_PARAMETER                     ; altsyncram_tmi1 ; Untyped                                             ;
+------------------------------------+-----------------+-----------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Tue Apr 08 21:18:56 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off jieinterlace -c jieinterlace
Info: Found 1 design units, including 1 entities, in source file jieinterlace.bdf
    Info: Found entity 1: jieinterlace
Info: Found 1 design units, including 1 entities, in source file jiaozhijiejiaozhi.bdf
    Info: Found entity 1: jiaozhijiejiaozhi
Info: Elaborating entity "jiaozhijiejiaozhi" for the top level hierarchy
Warning: Found multiple base names
Warning: Found multiple base names
Warning: Found multiple base names
Warning: Found multiple base names
Warning: Found multiple base names
Warning: Found multiple base names
Warning: Block or symbol "jieinterlace" of instance "inst2" overlaps another block or symbol
Info: Elaborating entity "jieinterlace" for hierarchy "jieinterlace:inst2"
Warning: Found multiple base names
Warning: Found multiple base names
Warning: Found multiple base names
Warning: Using design file RAM_MN_dual.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: RAM_MN_dual-beha
    Info: Found entity 1: RAM_MN_dual
Info: Elaborating entity "RAM_MN_dual" for hierarchy "jieinterlace:inst2|RAM_MN_dual:inst5"
Warning: Using design file counter.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: counter
Info: Elaborating entity "counter" for hierarchy "jieinterlace:inst2|counter:inst8"
Warning: Using design file rom_mn_interlace.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: rom_mn_interlace-beha
    Info: Found entity 1: rom_mn_interlace
Info: Elaborating entity "rom_mn_interlace" for hierarchy "jieinterlace:inst2|rom_mn_interlace:inst"
Warning: Using design file rom_mn_seq.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: rom_mn_seq-beha
    Info: Found entity 1: rom_mn_seq
Info: Elaborating entity "rom_mn_seq" for hierarchy "jieinterlace:inst2|rom_mn_seq:inst9"
Warning: Using design file RAM_MN_dual2.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: RAM_MN_dual2-beha
    Info: Found entity 1: RAM_MN_dual2
Info: Elaborating entity "RAM_MN_dual2" for hierarchy "jieinterlace:inst2|RAM_MN_dual2:inst6"
Warning: Using design file cobination.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: cobination
Info: Elaborating entity "cobination" for hierarchy "jieinterlace:inst2|cobination:inst12"
Warning: Using design file interlace.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: interlace
Info: Elaborating entity "interlace" for hierarchy "interlace:inst"
Warning: Found multiple base names
Warning: Found multiple base names
Warning: Found multiple base names
Warning: Using design file source.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: source-a
    Info: Found entity 1: source
Info: Elaborating entity "source" for hierarchy "interlace:inst|source:inst1"
Info: Duplicate registers merged to single register
    Info: Duplicate register "interlace:inst|rom_mn_interlace:inst|interlace_addr[0]" merged to single register "interlace:inst|rom_mn_seq:inst9|seq_addr[0]"
    Info: Duplicate register "jieinterlace:inst2|rom_mn_interlace:inst|interlace_addr[0]" merged to single register "jieinterlace:inst2|rom_mn_seq:inst9|seq_addr[0]"
Info: Duplicate registers merged to single register
    Info: Duplicate register "jieinterlace:inst2|rom_mn_seq:inst9|seq_addr[0]" merged to single register "interlace:inst|rom_mn_seq:inst9|seq_addr[0]"
    Info: Duplicate register "jieinterlace:inst2|rom_mn_seq:inst9|seq_addr[1]" merged to single register "interlace:inst|rom_mn_seq:inst9|seq_addr[1]"
    Info: Duplicate register "jieinterlace:inst2|rom_mn_seq:inst9|seq_addr[2]" merged to single register "interlace:inst|rom_mn_seq:inst9|seq_addr[2]"
    Info: Duplicate register "jieinterlace:inst2|rom_mn_seq:inst9|seq_addr[3]" merged to single register "interlace:inst|rom_mn_seq:inst9|seq_addr[3]"
    Info: Duplicate register "jieinterlace:inst2|rom_mn_seq:inst9|seq_addr[4]" merged to single register "interlace:inst|rom_mn_seq:inst9|seq_addr[4]"
    Info: Duplicate register "jieinterlace:inst2|counter:inst8|series_addr[3]" merged to single register "interlace:inst|counter:inst8|series_addr[3]"
    Info: Duplicate register "jieinterlace:inst2|counter:inst8|series_addr[2]" merged to single register "interlace:inst|counter:inst8|series_addr[2]"
    Info: Duplicate register "jieinterlace:inst2|counter:inst8|series_addr[1]" merged to single register "interlace:inst|counter:inst8|series_addr[1]"
    Info: Duplicate register "jieinterlace:inst2|counter:inst8|series_addr[0]" merged to single register "interlace:inst|counter:inst8|series_addr[0]"
    Info: Duplicate register "jieinterlace:inst2|counter:inst8|cnt[5]" merged to single register "interlace:inst|counter:inst8|cnt[5]"
    Info: Duplicate register "jieinterlace:inst2|counter:inst8|cnt[4]" merged to single register "interlace:inst|counter:inst8|cnt[4]"
    Info: Duplicate register "jieinterlace:inst2|counter:inst8|cnt[3]" merged to single register "interlace:inst|counter:inst8|cnt[3]"
    Info: Duplicate register "jieinterlace:inst2|counter:inst8|cnt[2]" merged to single register "interlace:inst|counter:inst8|cnt[2]"
    Info: Duplicate register "jieinterlace:inst2|counter:inst8|cnt[1]" merged to single register "interlace:inst|counter:inst8|cnt[1]"
    Info: Duplicate register "jieinterlace:inst2|counter:inst8|cnt[0]" merged to single register "interlace:inst|counter:inst8|cnt[0]"
    Info: Duplicate register "jieinterlace:inst2|counter:inst8|series_addr[4]" merged to single register "interlace:inst|counter:inst8|series_addr[4]"
Info: Duplicate registers merged to single register
    Info: Duplicate register "jieinterlace:inst2|rom_mn_interlace:inst|interlace_addr[1]" merged to single register "interlace:inst|rom_mn_interlace:inst|interlace_addr[1]"
    Info: Duplicate register "jieinterlace:inst2|rom_mn_interlace:inst|interlace_addr[2]" merged to single register "interlace:inst|rom_mn_interlace:inst|interlace_addr[2]"
    Info: Duplicate register "jieinterlace:inst2|rom_mn_interlace:inst|interlace_addr[3]" merged to single register "interlace:inst|rom_mn_interlace:inst|interlace_addr[3]"
    Info: Duplicate register "jieinterlace:inst2|rom_mn_interlace:inst|interlace_addr[4]" merged to single register "interlace:inst|rom_mn_interlace:inst|interlace_addr[4]"
Warning: Created node "jieinterlace:inst2|RAM_MN_dual2:inst6|ram[0]~60" as a RAM by generating altsyncram megafunction to implement register logic with M512 or M4K memory block or M-RAM. Pass-through logic has been added.
Warning: Created node "jieinterlace:inst2|RAM_MN_dual:inst5|ram[0]~60" as a RAM by generating altsyncram megafunction to implement register logic with M512 or M4K memory block or M-RAM. Pass-through logic has been added.
Info: Duplicate registers merged to single register
    Info: Duplicate register "jieinterlace:inst2|RAM_MN_dual2:inst6|Mux0~49" merged to single register "interlace:inst|rom_mn_seq:inst9|seq_addr[0]"
    Info: Duplicate register "jieinterlace:inst2|RAM_MN_dual:inst5|Mux0~49" merged to single register "interlace:inst|rom_mn_seq:inst9|seq_addr[0]"
    Info: Duplicate register "jieinterlace:inst2|RAM_MN_dual:inst5|Mux0~48" merged to single register "jieinterlace:inst2|RAM_MN_dual2:inst6|Mux0~48"
    Info: Duplicate register "jieinterlace:inst2|RAM_MN_dual:inst5|Mux0~51" merged to single register "jieinterlace:inst2|RAM_MN_dual2:inst6|Mux0~51"
    Info: Duplicate register "jieinterlace:inst2|RAM_MN_dual:inst5|Mux0~52" merged to single register "jieinterlace:inst2|RAM_MN_dual2:inst6|Mux0~52"
    Info: Duplicate register "jieinterlace:inst2|RAM_MN_dual:inst5|Mux0~54" merged to single register "jieinterlace:inst2|RAM_MN_dual2:inst6|Mux0~54"
    Info: Duplicate register "jieinterlace:inst2|RAM_MN_dual:inst5|Mux0~55" merged to single register "jieinterlace:inst2|RAM_MN_dual2:inst6|Mux0~55"
    Info: Duplicate register "jieinterlace:inst2|RAM_MN_dual:inst5|Mux0~57" merged to single register "jieinterlace:inst2|RAM_MN_dual2:inst6|Mux0~57"
    Info: Duplicate register "jieinterlace:inst2|RAM_MN_dual:inst5|Mux0~58" merged to single register "jieinterlace:inst2|RAM_MN_dual2:inst6|Mux0~58"
    Info: Duplicate register "jieinterlace:inst2|RAM_MN_dual:inst5|Mux0~60" merged to single register "jieinterlace:inst2|RAM_MN_dual2:inst6|Mux0~60"
    Info: Duplicate register "jieinterlace:inst2|RAM_MN_dual:inst5|Mux0~61" merged to single register "jieinterlace:inst2|RAM_MN_dual2:inst6|Mux0~61"
    Info: Duplicate register "jieinterlace:inst2|RAM_MN_dual:inst5|Mux0~63" merged to single register "jieinterlace:inst2|RAM_MN_dual2:inst6|Mux0~63"
    Info: Duplicate register "jieinterlace:inst2|RAM_MN_dual:inst5|Mux0~65" merged to single register "jieinterlace:inst2|RAM_MN_dual2:inst6|Mux0~65"
Info: Duplicate registers merged to single register
    Info: Duplicate register "interlace:inst|source:inst1|m[0]" merged to single register "interlace:inst|counter:inst8|series_addr[0]"
    Info: Duplicate register "interlace:inst|counter:inst8|cnt[0]" merged to single register "interlace:inst|counter:inst8|series_addr[0]"
    Info: Duplicate register "interlace:inst|source:inst1|m[1]" merged to single register "interlace:inst|counter:inst8|cnt[1]"
Info: Inferred 2 megafunctions from design logic
    Info: Inferred altsyncram megafunction (NUMWORDS_A=32, WIDTH_A=2) from the following design logic: "jieinterlace:inst2|RAM_MN_dual2:inst6|ram[0]~60"
    Info: Inferred altsyncram megafunction (NUMWORDS_A=32, WIDTH_A=2) from the following design logic: "jieinterlace:inst2|RAM_MN_dual:inst5|ram[0]~60"
Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus60/libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Info: Elaborated megafunction instantiation "jieinterlace:inst2|RAM_MN_dual2:inst6|altsyncram:ram_rtl_0"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_tmi1.tdf
    Info: Found entity 1: altsyncram_tmi1
Info: Implemented 57 device resources after synthesis - the final resource count might be different
    Info: Implemented 1 input pins
    Info: Implemented 6 output pins
    Info: Implemented 46 logic cells
    Info: Implemented 4 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 23 warnings
    Info: Processing ended: Tue Apr 08 21:18:58 2008
    Info: Elapsed time: 00:00:03