jie_counter.v

来自「一个简单的交织实现程序」· Verilog 代码 · 共 29 行

module jie_counter(clk,series_addr,ch,clr );
  input clk ;
  output  [3:0] series_addr;
  reg     [3:0] series_addr;
  output reg ch ,clr;
  reg [8:0] cnt;
parameter NN=16; //m= 4,n=4 ;NN=m*n
always @(posedge clk  )
    if (series_addr==NN-1  )
        begin 
        series_addr<=8'b0;   
         clr <= 1'b1;   
         end       
 	else  
	    begin
	    series_addr<=series_addr+8'b1;      
         clr <= 1'b0;  
		end 
always @(posedge clk  )
    if (cnt==2*NN-1  )
       cnt<=9'b0;            
 	else  
	   cnt<=cnt+9'b1;      
       
always @(cnt)
  if (cnt<=NN-1) 
      ch<=1'b1;
   else ch<=1'b0;
 endmodule