interlace.fit.summary

来自「一个简单的交织实现程序」· SUMMARY 代码 · 共 16 行

Fitter Status : Successful - Mon Apr 07 22:22:38 2008
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : interlace
Top-level Entity Name : interlace
Family : Stratix II
Device : EP2S60F672C3
Timing Models : Final
Total ALUTs : 37 / 48,352 ( < 1 % )
Total registers : 32
Total pins : 21 / 493 ( 4 % )
Total virtual pins : 0
Total memory bits : 64 / 2,544,192 ( < 1 % )
DSP block 9-bit elements : 0 / 288 ( 0 % )
Total PLLs : 0 / 6 ( 0 % )
Total DLLs : 0 / 2 ( 0 % )