interlace.map.eqn

一个简单的交织实现程序

--L1L34 is jie_RAM_MN_dual2:inst10|ram[2]~1602
L1L34 = inst14 & (L1L2 & E1L1 # !L1L2 & (L1_ram[2])) # !inst14 & (L1_ram[2]);


--L1L3 is jie_RAM_MN_dual2:inst10|Decoder~323
L1L3 = !K1_seq_addr[2] & !K1_seq_addr[3] & !C1_series_addr[0] & K1_seq_addr[1];


--L1L30 is jie_RAM_MN_dual2:inst10|ram[0]~1603
L1L30 = inst14 & (L1L3 & E1L1 # !L1L3 & (L1_ram[0])) # !inst14 & (L1_ram[0]);


--L1L4 is jie_RAM_MN_dual2:inst10|Decoder~324
L1L4 = !K1_seq_addr[2] & K1_seq_addr[3] & C1_series_addr[0] & K1_seq_addr[1];


--L1L42 is jie_RAM_MN_dual2:inst10|ram[6]~1604
L1L42 = inst14 & (L1L4 & E1L1 # !L1L4 & (L1_ram[6])) # !inst14 & (L1_ram[6]);


--L1L5 is jie_RAM_MN_dual2:inst10|Decoder~325
L1L5 = K1_seq_addr[2] & !K1_seq_addr[3] & C1_series_addr[0] & !K1_seq_addr[1];


--L1L56 is jie_RAM_MN_dual2:inst10|ram[13]~1605
L1L56 = inst14 & (L1L5 & E1L1 # !L1L5 & (L1_ram[13])) # !inst14 & (L1_ram[13]);


--L1L6 is jie_RAM_MN_dual2:inst10|Decoder~326
L1L6 = K1_seq_addr[2] & K1_seq_addr[3] & !C1_series_addr[0] & !K1_seq_addr[1];


--L1L52 is jie_RAM_MN_dual2:inst10|ram[11]~1606
L1L52 = inst14 & (L1L6 & E1L1 # !L1L6 & (L1_ram[11])) # !inst14 & (L1_ram[11]);


--L1L7 is jie_RAM_MN_dual2:inst10|Decoder~327
L1L7 = K1_seq_addr[2] & !K1_seq_addr[3] & !C1_series_addr[0] & !K1_seq_addr[1];


--L1L48 is jie_RAM_MN_dual2:inst10|ram[9]~1607
L1L48 = inst14 & (L1L7 & E1L1 # !L1L7 & (L1_ram[9])) # !inst14 & (L1_ram[9]);


--L1L8 is jie_RAM_MN_dual2:inst10|Decoder~328
L1L8 = K1_seq_addr[2] & K1_seq_addr[3] & C1_series_addr[0] & !K1_seq_addr[1];


--L1L60 is jie_RAM_MN_dual2:inst10|ram[15]~1608
L1L60 = inst14 & (L1L8 & E1L1 # !L1L8 & (L1_ram[15])) # !inst14 & (L1_ram[15]);


--L1L9 is jie_RAM_MN_dual2:inst10|Decoder~329
L1L9 = K1_seq_addr[2] & !K1_seq_addr[3] & C1_series_addr[0] & K1_seq_addr[1];


--L1L40 is jie_RAM_MN_dual2:inst10|ram[5]~1609
L1L40 = inst14 & (L1L9 & E1L1 # !L1L9 & (L1_ram[5])) # !inst14 & (L1_ram[5]);


--L1L10 is jie_RAM_MN_dual2:inst10|Decoder~330
L1L10 = K1_seq_addr[2] & K1_seq_addr[3] & !C1_series_addr[0] & K1_seq_addr[1];


--L1L36 is jie_RAM_MN_dual2:inst10|ram[3]~1610
L1L36 = inst14 & (L1L10 & E1L1 # !L1L10 & (L1_ram[3])) # !inst14 & (L1_ram[3]);


--L1L11 is jie_RAM_MN_dual2:inst10|Decoder~331
L1L11 = K1_seq_addr[2] & !K1_seq_addr[3] & !C1_series_addr[0] & K1_seq_addr[1];


--L1L32 is jie_RAM_MN_dual2:inst10|ram[1]~1611
L1L32 = inst14 & (L1L11 & E1L1 # !L1L11 & (L1_ram[1])) # !inst14 & (L1_ram[1]);


--L1L12 is jie_RAM_MN_dual2:inst10|Decoder~332
L1L12 = K1_seq_addr[2] & K1_seq_addr[3] & C1_series_addr[0] & K1_seq_addr[1];


--L1L44 is jie_RAM_MN_dual2:inst10|ram[7]~1612
L1L44 = inst14 & (L1L12 & E1L1 # !L1L12 & (L1_ram[7])) # !inst14 & (L1_ram[7]);


--L1L13 is jie_RAM_MN_dual2:inst10|Decoder~333
L1L13 = !K1_seq_addr[2] & !K1_seq_addr[3] & C1_series_addr[0] & !K1_seq_addr[1];


--L1L54 is jie_RAM_MN_dual2:inst10|ram[12]~1613
L1L54 = inst14 & (L1L13 & E1L1 # !L1L13 & (L1_ram[12])) # !inst14 & (L1_ram[12]);


--L1L14 is jie_RAM_MN_dual2:inst10|Decoder~334
L1L14 = !K1_seq_addr[2] & K1_seq_addr[3] & !C1_series_addr[0] & !K1_seq_addr[1];


--L1L50 is jie_RAM_MN_dual2:inst10|ram[10]~1614
L1L50 = inst14 & (L1L14 & E1L1 # !L1L14 & (L1_ram[10])) # !inst14 & (L1_ram[10]);


--L1L15 is jie_RAM_MN_dual2:inst10|Decoder~335
L1L15 = !K1_seq_addr[2] & !K1_seq_addr[3] & !C1_series_addr[0] & !K1_seq_addr[1];


--L1L46 is jie_RAM_MN_dual2:inst10|ram[8]~1615
L1L46 = inst14 & (L1L15 & E1L1 # !L1L15 & (L1_ram[8])) # !inst14 & (L1_ram[8]);


--L1L16 is jie_RAM_MN_dual2:inst10|Decoder~336
L1L16 = !K1_seq_addr[2] & K1_seq_addr[3] & C1_series_addr[0] & !K1_seq_addr[1];


--L1L58 is jie_RAM_MN_dual2:inst10|ram[14]~1616
L1L58 = inst14 & (L1L16 & E1L1 # !L1L16 & (L1_ram[14])) # !inst14 & (L1_ram[14]);


--D1L30 is jie_RAM_MN_dual:inst2|ram[8]~1601
D1L30 = L1L15 & (inst14 & D1_ram[8] # !inst14 & (E1L1)) # !L1L15 & D1_ram[8];


--D1L36 is jie_RAM_MN_dual:inst2|ram[11]~1602
D1L36 = L1L6 & (inst14 & D1_ram[11] # !inst14 & (E1L1)) # !L1L6 & D1_ram[11];


--D1L32 is jie_RAM_MN_dual:inst2|ram[9]~1603
D1L32 = L1L7 & (inst14 & D1_ram[9] # !inst14 & (E1L1)) # !L1L7 & D1_ram[9];


--D1L34 is jie_RAM_MN_dual:inst2|ram[10]~1604
D1L34 = L1L14 & (inst14 & D1_ram[10] # !inst14 & (E1L1)) # !L1L14 & D1_ram[10];


--D1L22 is jie_RAM_MN_dual:inst2|ram[4]~1605
D1L22 = L1L1 & (inst14 & D1_ram[4] # !inst14 & (E1L1)) # !L1L1 & D1_ram[4];


--D1L28 is jie_RAM_MN_dual:inst2|ram[7]~1606
D1L28 = L1L12 & (inst14 & D1_ram[7] # !inst14 & (E1L1)) # !L1L12 & D1_ram[7];


--D1L24 is jie_RAM_MN_dual:inst2|ram[5]~1607
D1L24 = L1L9 & (inst14 & D1_ram[5] # !inst14 & (E1L1)) # !L1L9 & D1_ram[5];


--D1L26 is jie_RAM_MN_dual:inst2|ram[6]~1608
D1L26 = L1L4 & (inst14 & D1_ram[6] # !inst14 & (E1L1)) # !L1L4 & D1_ram[6];


--D1L14 is jie_RAM_MN_dual:inst2|ram[0]~1609
D1L14 = L1L3 & (inst14 & D1_ram[0] # !inst14 & (E1L1)) # !L1L3 & D1_ram[0];


--D1L20 is jie_RAM_MN_dual:inst2|ram[3]~1610
D1L20 = L1L10 & (inst14 & D1_ram[3] # !inst14 & (E1L1)) # !L1L10 & D1_ram[3];


--D1L16 is jie_RAM_MN_dual:inst2|ram[1]~1611
D1L16 = L1L11 & (inst14 & D1_ram[1] # !inst14 & (E1L1)) # !L1L11 & D1_ram[1];


--D1L18 is jie_RAM_MN_dual:inst2|ram[2]~1612
D1L18 = L1L2 & (inst14 & D1_ram[2] # !inst14 & (E1L1)) # !L1L2 & D1_ram[2];


--D1L38 is jie_RAM_MN_dual:inst2|ram[12]~1613
D1L38 = L1L13 & (inst14 & D1_ram[12] # !inst14 & (E1L1)) # !L1L13 & D1_ram[12];


--D1L44 is jie_RAM_MN_dual:inst2|ram[15]~1614
D1L44 = L1L8 & (inst14 & D1_ram[15] # !inst14 & (E1L1)) # !L1L8 & D1_ram[15];


--D1L40 is jie_RAM_MN_dual:inst2|ram[13]~1615
D1L40 = L1L5 & (inst14 & D1_ram[13] # !inst14 & (E1L1)) # !L1L5 & D1_ram[13];


--D1L42 is jie_RAM_MN_dual:inst2|ram[14]~1616
D1L42 = L1L16 & (inst14 & D1_ram[14] # !inst14 & (E1L1)) # !L1L16 & D1_ram[14];


--C1L4 is jie_counter:inst1|add~219
C1L4 = CARRY(!C1L2 # !C1_series_addr[2]);


--C1L6 is jie_counter:inst1|add~221
C1L6 = CARRY(C1_series_addr[3] & !C1L4);


--C1L7 is jie_counter:inst1|add~222
C1L7 = C1_cnt[4] & !C1L6 # !C1_cnt[4] & (C1L6 # GND);

--C1L8 is jie_counter:inst1|add~223
C1L8 = CARRY(!C1L6 # !C1_cnt[4]);


--C1L9 is jie_counter:inst1|add~224
C1L9 = C1_cnt[5] & (C1L8 $ GND) # !C1_cnt[5] & !C1L8 & VCC;

--C1L10 is jie_counter:inst1|add~225
C1L10 = CARRY(C1_cnt[5] & !C1L8);


--C1L11 is jie_counter:inst1|add~226
C1L11 = C1_cnt[6] & !C1L10 # !C1_cnt[6] & (C1L10 # GND);

--C1L12 is jie_counter:inst1|add~227
C1L12 = CARRY(!C1L10 # !C1_cnt[6]);


--C1L13 is jie_counter:inst1|add~228
C1L13 = C1_cnt[7] & (C1L12 $ GND) # !C1_cnt[7] & !C1L12 & VCC;

--C1L14 is jie_counter:inst1|add~229
C1L14 = CARRY(C1_cnt[7] & !C1L12);


--C1L15 is jie_counter:inst1|add~230
C1L15 = C1_cnt[8] $ C1L14;


--A1L22 is rtl~54
A1L22 = C1_series_addr[3] & C1_series_addr[2] & C1_series_addr[1] & C1_series_addr[0];


--C1L23 is jie_counter:inst1|cnt~90
C1L23 = C1L9 & (!A1L22 # !A1L21 # !C1_cnt[4]);


--C1L26 is jie_counter:inst1|series_addr[0]~62
C1L26 = !C1_series_addr[0];


--clk is clk
--operation mode is input

clk = INPUT();


--datain is datain
--operation mode is input

datain = INPUT();


--d1 is d1
--operation mode is output

d1 = OUTPUT(G1_dout);


--d2 is d2
--operation mode is output

d2 = OUTPUT(H1_dout);


--dataout is dataout
--operation mode is output

dataout = OUTPUT(E1L1);


--DOUT is DOUT
--operation mode is output

DOUT = OUTPUT(E2L1);


--d11 is d11
--operation mode is output

d11 = OUTPUT(D1_dout);


--d22 is d22
--operation mode is output

d22 = OUTPUT(L1_dout);


--ch2 is ch2
--operation mode is output

ch2 = OUTPUT(inst14);


--rw_control is rw_control
--operation mode is output

rw_control = OUTPUT(inst14);


--cnt[3] is cnt[3]
--operation mode is output

cnt[3] = OUTPUT(C1_series_addr[3]);


--cnt[2] is cnt[2]
--operation mode is output

cnt[2] = OUTPUT(C1_series_addr[2]);


--cnt[1] is cnt[1]
--operation mode is output

cnt[1] = OUTPUT(C1_series_addr[1]);


--cnt[0] is cnt[0]
--operation mode is output

cnt[0] = OUTPUT(C1_series_addr[0]);


--interlace_addr[3] is interlace_addr[3]
--operation mode is output

interlace_addr[3] = OUTPUT(K1_seq_addr[3]);


--interlace_addr[2] is interlace_addr[2]
--operation mode is output

interlace_addr[2] = OUTPUT(K1_seq_addr[2]);


--interlace_addr[1] is interlace_addr[1]
--operation mode is output

interlace_addr[1] = OUTPUT(K1_seq_addr[1]);


--interlace_addr[0] is interlace_addr[0]
--operation mode is output

interlace_addr[0] = OUTPUT(!C1_series_addr[0]);


--sequence_addr[3] is sequence_addr[3]
--operation mode is output

sequence_addr[3] = OUTPUT(!K1_seq_addr[1]);


--sequence_addr[2] is sequence_addr[2]
--operation mode is output

sequence_addr[2] = OUTPUT(C1_series_addr[0]);


--sequence_addr[1] is sequence_addr[1]
--operation mode is output

sequence_addr[1] = OUTPUT(K1_seq_addr[3]);


--sequence_addr[0] is sequence_addr[0]
--operation mode is output

sequence_addr[0] = OUTPUT(K1_seq_addr[2]);