interlace.map.eqn

一个简单的交织实现程序

L1L25 = K1_seq_addr[2] & (K1_seq_addr[1]) # !K1_seq_addr[2] & (K1_seq_addr[1] & L1_ram[10] # !K1_seq_addr[1] & (L1_ram[8]));


--L1_ram[14] is jie_RAM_MN_dual2:inst10|ram[14]
L1_ram[14] = DFFEAS(L1L58, clk,  ,  ,  ,  ,  ,  ,  );


--L1L26 is jie_RAM_MN_dual2:inst10|Mux~64
L1L26 = K1_seq_addr[2] & (L1L25 & (L1_ram[14]) # !L1L25 & L1_ram[12]) # !K1_seq_addr[2] & (L1L25);


--L1L27 is jie_RAM_MN_dual2:inst10|Mux~65
L1L27 = C1_series_addr[0] & (L1L24 & (L1L26) # !L1L24 & L1L19) # !C1_series_addr[0] & (L1L24);


--D1_ram[8] is jie_RAM_MN_dual:inst2|ram[8]
D1_ram[8] = DFFEAS(D1L30, clk,  ,  ,  ,  ,  ,  ,  );


--D1_ram[11] is jie_RAM_MN_dual:inst2|ram[11]
D1_ram[11] = DFFEAS(D1L36, clk,  ,  ,  ,  ,  ,  ,  );


--D1_ram[9] is jie_RAM_MN_dual:inst2|ram[9]
D1_ram[9] = DFFEAS(D1L32, clk,  ,  ,  ,  ,  ,  ,  );


--D1L2 is jie_RAM_MN_dual:inst2|Mux~56
D1L2 = C1_series_addr[0] & (K1_seq_addr[1]) # !C1_series_addr[0] & (K1_seq_addr[1] & D1_ram[11] # !K1_seq_addr[1] & (D1_ram[9]));


--D1_ram[10] is jie_RAM_MN_dual:inst2|ram[10]
D1_ram[10] = DFFEAS(D1L34, clk,  ,  ,  ,  ,  ,  ,  );


--D1L3 is jie_RAM_MN_dual:inst2|Mux~57
D1L3 = C1_series_addr[0] & (D1L2 & (D1_ram[10]) # !D1L2 & D1_ram[8]) # !C1_series_addr[0] & (D1L2);


--D1_ram[4] is jie_RAM_MN_dual:inst2|ram[4]
D1_ram[4] = DFFEAS(D1L22, clk,  ,  ,  ,  ,  ,  ,  );


--D1_ram[7] is jie_RAM_MN_dual:inst2|ram[7]
D1_ram[7] = DFFEAS(D1L28, clk,  ,  ,  ,  ,  ,  ,  );


--D1_ram[5] is jie_RAM_MN_dual:inst2|ram[5]
D1_ram[5] = DFFEAS(D1L24, clk,  ,  ,  ,  ,  ,  ,  );


--D1L4 is jie_RAM_MN_dual:inst2|Mux~58
D1L4 = C1_series_addr[0] & (K1_seq_addr[1]) # !C1_series_addr[0] & (K1_seq_addr[1] & D1_ram[7] # !K1_seq_addr[1] & (D1_ram[5]));


--D1_ram[6] is jie_RAM_MN_dual:inst2|ram[6]
D1_ram[6] = DFFEAS(D1L26, clk,  ,  ,  ,  ,  ,  ,  );


--D1L5 is jie_RAM_MN_dual:inst2|Mux~59
D1L5 = C1_series_addr[0] & (D1L4 & (D1_ram[6]) # !D1L4 & D1_ram[4]) # !C1_series_addr[0] & (D1L4);


--D1_ram[0] is jie_RAM_MN_dual:inst2|ram[0]
D1_ram[0] = DFFEAS(D1L14, clk,  ,  ,  ,  ,  ,  ,  );


--D1_ram[3] is jie_RAM_MN_dual:inst2|ram[3]
D1_ram[3] = DFFEAS(D1L20, clk,  ,  ,  ,  ,  ,  ,  );


--D1_ram[1] is jie_RAM_MN_dual:inst2|ram[1]
D1_ram[1] = DFFEAS(D1L16, clk,  ,  ,  ,  ,  ,  ,  );


--D1L6 is jie_RAM_MN_dual:inst2|Mux~60
D1L6 = C1_series_addr[0] & (K1_seq_addr[1]) # !C1_series_addr[0] & (K1_seq_addr[1] & D1_ram[3] # !K1_seq_addr[1] & (D1_ram[1]));


--D1_ram[2] is jie_RAM_MN_dual:inst2|ram[2]
D1_ram[2] = DFFEAS(D1L18, clk,  ,  ,  ,  ,  ,  ,  );


--D1L7 is jie_RAM_MN_dual:inst2|Mux~61
D1L7 = C1_series_addr[0] & (D1L6 & (D1_ram[2]) # !D1L6 & D1_ram[0]) # !C1_series_addr[0] & (D1L6);


--D1L8 is jie_RAM_MN_dual:inst2|Mux~62
D1L8 = K1_seq_addr[3] & (K1_seq_addr[2]) # !K1_seq_addr[3] & (K1_seq_addr[2] & D1L5 # !K1_seq_addr[2] & (D1L7));


--D1_ram[12] is jie_RAM_MN_dual:inst2|ram[12]
D1_ram[12] = DFFEAS(D1L38, clk,  ,  ,  ,  ,  ,  ,  );


--D1_ram[15] is jie_RAM_MN_dual:inst2|ram[15]
D1_ram[15] = DFFEAS(D1L44, clk,  ,  ,  ,  ,  ,  ,  );


--D1_ram[13] is jie_RAM_MN_dual:inst2|ram[13]
D1_ram[13] = DFFEAS(D1L40, clk,  ,  ,  ,  ,  ,  ,  );


--D1L9 is jie_RAM_MN_dual:inst2|Mux~63
D1L9 = C1_series_addr[0] & (K1_seq_addr[1]) # !C1_series_addr[0] & (K1_seq_addr[1] & D1_ram[15] # !K1_seq_addr[1] & (D1_ram[13]));


--D1_ram[14] is jie_RAM_MN_dual:inst2|ram[14]
D1_ram[14] = DFFEAS(D1L42, clk,  ,  ,  ,  ,  ,  ,  );


--D1L10 is jie_RAM_MN_dual:inst2|Mux~64
D1L10 = C1_series_addr[0] & (D1L9 & (D1_ram[14]) # !D1L9 & D1_ram[12]) # !C1_series_addr[0] & (D1L9);


--D1L11 is jie_RAM_MN_dual:inst2|Mux~65
D1L11 = K1_seq_addr[3] & (D1L8 & (D1L10) # !D1L8 & D1L3) # !K1_seq_addr[3] & (D1L8);


--C1_cnt[4] is jie_counter:inst1|cnt[4]
C1_cnt[4] = DFFEAS(C1L7, clk,  ,  ,  ,  ,  ,  ,  );


--C1_cnt[8] is jie_counter:inst1|cnt[8]
C1_cnt[8] = DFFEAS(C1L15, clk,  ,  ,  ,  ,  ,  ,  );


--C1_cnt[7] is jie_counter:inst1|cnt[7]
C1_cnt[7] = DFFEAS(C1L13, clk,  ,  ,  ,  ,  ,  ,  );


--C1_cnt[6] is jie_counter:inst1|cnt[6]
C1_cnt[6] = DFFEAS(C1L11, clk,  ,  ,  ,  ,  ,  ,  );


--C1_cnt[5] is jie_counter:inst1|cnt[5]
C1_cnt[5] = DFFEAS(C1L23, clk,  ,  ,  ,  ,  ,  ,  );


--A1L21 is rtl~53
A1L21 = !C1_cnt[8] & !C1_cnt[7] & !C1_cnt[6] & !C1_cnt[5];


--J1L1 is counter:inst8|ch~36
J1L1 = !C1_cnt[4] & A1L21;


--C1L31 is jie_counter:inst1|series_addr[3]~60
C1L31 = C1_series_addr[3] $ (C1_series_addr[2] & C1_series_addr[1] & C1_series_addr[0]);


--C1L29 is jie_counter:inst1|series_addr[2]~61
C1L29 = C1_series_addr[2] $ (C1_series_addr[1] & C1_series_addr[0]);


--C1L1 is jie_counter:inst1|add~216
C1L1 = C1_series_addr[0] & (C1_series_addr[1] $ VCC) # !C1_series_addr[0] & C1_series_addr[1] & VCC;

--C1L2 is jie_counter:inst1|add~217
C1L2 = CARRY(C1_series_addr[0] & C1_series_addr[1]);


--G1L1 is RAM_MN_dual:inst5|Decoder~241
G1L1 = C1_series_addr[0] & K1_seq_addr[1] & K1_seq_addr[2] & K1_seq_addr[3];


--G1L58 is RAM_MN_dual:inst5|ram[14]~961
G1L58 = inst14 & (G1L1 & datain # !G1L1 & (G1_ram[14])) # !inst14 & (G1_ram[14]);


--G1L2 is RAM_MN_dual:inst5|Decoder~242
G1L2 = !C1_series_addr[0] & !K1_seq_addr[1] & K1_seq_addr[2] & K1_seq_addr[3];


--G1L56 is RAM_MN_dual:inst5|ram[13]~962
G1L56 = inst14 & (G1L2 & datain # !G1L2 & (G1_ram[13])) # !inst14 & (G1_ram[13]);


--G1L3 is RAM_MN_dual:inst5|Decoder~243
G1L3 = C1_series_addr[0] & !K1_seq_addr[1] & K1_seq_addr[2] & K1_seq_addr[3];


--G1L54 is RAM_MN_dual:inst5|ram[12]~963
G1L54 = inst14 & (G1L3 & datain # !G1L3 & (G1_ram[12])) # !inst14 & (G1_ram[12]);


--G1L4 is RAM_MN_dual:inst5|Decoder~244
G1L4 = !C1_series_addr[0] & K1_seq_addr[1] & K1_seq_addr[2] & K1_seq_addr[3];


--G1L60 is RAM_MN_dual:inst5|ram[15]~964
G1L60 = inst14 & (G1L4 & datain # !G1L4 & (G1_ram[15])) # !inst14 & (G1_ram[15]);


--G1L5 is RAM_MN_dual:inst5|Decoder~245
G1L5 = !C1_series_addr[0] & !K1_seq_addr[1] & !K1_seq_addr[2] & !K1_seq_addr[3];


--G1L32 is RAM_MN_dual:inst5|ram[1]~965
G1L32 = inst14 & (G1L5 & datain # !G1L5 & (G1_ram[1])) # !inst14 & (G1_ram[1]);


--G1L6 is RAM_MN_dual:inst5|Decoder~246
G1L6 = C1_series_addr[0] & K1_seq_addr[1] & !K1_seq_addr[2] & !K1_seq_addr[3];


--G1L34 is RAM_MN_dual:inst5|ram[2]~966
G1L34 = inst14 & (G1L6 & datain # !G1L6 & (G1_ram[2])) # !inst14 & (G1_ram[2]);


--G1L7 is RAM_MN_dual:inst5|Decoder~247
G1L7 = C1_series_addr[0] & !K1_seq_addr[1] & !K1_seq_addr[2] & !K1_seq_addr[3];


--G1L30 is RAM_MN_dual:inst5|ram[0]~967
G1L30 = inst14 & (G1L7 & datain # !G1L7 & (G1_ram[0])) # !inst14 & (G1_ram[0]);


--G1L8 is RAM_MN_dual:inst5|Decoder~248
G1L8 = !C1_series_addr[0] & K1_seq_addr[1] & !K1_seq_addr[2] & !K1_seq_addr[3];


--G1L36 is RAM_MN_dual:inst5|ram[3]~968
G1L36 = inst14 & (G1L8 & datain # !G1L8 & (G1_ram[3])) # !inst14 & (G1_ram[3]);


--G1L9 is RAM_MN_dual:inst5|Decoder~249
G1L9 = C1_series_addr[0] & K1_seq_addr[1] & !K1_seq_addr[2] & K1_seq_addr[3];


--G1L50 is RAM_MN_dual:inst5|ram[10]~969
G1L50 = inst14 & (G1L9 & datain # !G1L9 & (G1_ram[10])) # !inst14 & (G1_ram[10]);


--G1L10 is RAM_MN_dual:inst5|Decoder~250
G1L10 = !C1_series_addr[0] & !K1_seq_addr[1] & !K1_seq_addr[2] & K1_seq_addr[3];


--G1L48 is RAM_MN_dual:inst5|ram[9]~970
G1L48 = inst14 & (G1L10 & datain # !G1L10 & (G1_ram[9])) # !inst14 & (G1_ram[9]);


--G1L11 is RAM_MN_dual:inst5|Decoder~251
G1L11 = C1_series_addr[0] & !K1_seq_addr[1] & !K1_seq_addr[2] & K1_seq_addr[3];


--G1L46 is RAM_MN_dual:inst5|ram[8]~971
G1L46 = inst14 & (G1L11 & datain # !G1L11 & (G1_ram[8])) # !inst14 & (G1_ram[8]);


--G1L12 is RAM_MN_dual:inst5|Decoder~252
G1L12 = !C1_series_addr[0] & K1_seq_addr[1] & !K1_seq_addr[2] & K1_seq_addr[3];


--G1L52 is RAM_MN_dual:inst5|ram[11]~972
G1L52 = inst14 & (G1L12 & datain # !G1L12 & (G1_ram[11])) # !inst14 & (G1_ram[11]);


--G1L13 is RAM_MN_dual:inst5|Decoder~253
G1L13 = !C1_series_addr[0] & !K1_seq_addr[1] & K1_seq_addr[2] & !K1_seq_addr[3];


--G1L40 is RAM_MN_dual:inst5|ram[5]~973
G1L40 = inst14 & (G1L13 & datain # !G1L13 & (G1_ram[5])) # !inst14 & (G1_ram[5]);


--G1L14 is RAM_MN_dual:inst5|Decoder~254
G1L14 = C1_series_addr[0] & K1_seq_addr[1] & K1_seq_addr[2] & !K1_seq_addr[3];


--G1L42 is RAM_MN_dual:inst5|ram[6]~974
G1L42 = inst14 & (G1L14 & datain # !G1L14 & (G1_ram[6])) # !inst14 & (G1_ram[6]);


--G1L15 is RAM_MN_dual:inst5|Decoder~255
G1L15 = C1_series_addr[0] & !K1_seq_addr[1] & K1_seq_addr[2] & !K1_seq_addr[3];


--G1L38 is RAM_MN_dual:inst5|ram[4]~975
G1L38 = inst14 & (G1L15 & datain # !G1L15 & (G1_ram[4])) # !inst14 & (G1_ram[4]);


--G1L16 is RAM_MN_dual:inst5|Decoder~256
G1L16 = !C1_series_addr[0] & K1_seq_addr[1] & K1_seq_addr[2] & !K1_seq_addr[3];


--G1L44 is RAM_MN_dual:inst5|ram[7]~976
G1L44 = inst14 & (G1L16 & datain # !G1L16 & (G1_ram[7])) # !inst14 & (G1_ram[7]);


--H1L22 is RAM_MN_dual2:inst6|ram[4]~961
H1L22 = G1L15 & (inst14 & H1_ram[4] # !inst14 & (datain)) # !G1L15 & H1_ram[4];


--H1L42 is RAM_MN_dual2:inst6|ram[14]~962
H1L42 = G1L1 & (inst14 & H1_ram[14] # !inst14 & (datain)) # !G1L1 & H1_ram[14];


--H1L38 is RAM_MN_dual2:inst6|ram[12]~963
H1L38 = G1L3 & (inst14 & H1_ram[12] # !inst14 & (datain)) # !G1L3 & H1_ram[12];


--H1L26 is RAM_MN_dual2:inst6|ram[6]~964
H1L26 = G1L14 & (inst14 & H1_ram[6] # !inst14 & (datain)) # !G1L14 & H1_ram[6];


--H1L16 is RAM_MN_dual2:inst6|ram[1]~965
H1L16 = G1L5 & (inst14 & H1_ram[1] # !inst14 & (datain)) # !G1L5 & H1_ram[1];


--H1L36 is RAM_MN_dual2:inst6|ram[11]~966
H1L36 = G1L12 & (inst14 & H1_ram[11] # !inst14 & (datain)) # !G1L12 & H1_ram[11];


--H1L32 is RAM_MN_dual2:inst6|ram[9]~967
H1L32 = G1L10 & (inst14 & H1_ram[9] # !inst14 & (datain)) # !G1L10 & H1_ram[9];


--H1L20 is RAM_MN_dual2:inst6|ram[3]~968
H1L20 = G1L8 & (inst14 & H1_ram[3] # !inst14 & (datain)) # !G1L8 & H1_ram[3];


--H1L14 is RAM_MN_dual2:inst6|ram[0]~969
H1L14 = G1L7 & (inst14 & H1_ram[0] # !inst14 & (datain)) # !G1L7 & H1_ram[0];


--H1L34 is RAM_MN_dual2:inst6|ram[10]~970
H1L34 = G1L9 & (inst14 & H1_ram[10] # !inst14 & (datain)) # !G1L9 & H1_ram[10];


--H1L30 is RAM_MN_dual2:inst6|ram[8]~971
H1L30 = G1L11 & (inst14 & H1_ram[8] # !inst14 & (datain)) # !G1L11 & H1_ram[8];


--H1L18 is RAM_MN_dual2:inst6|ram[2]~972
H1L18 = G1L6 & (inst14 & H1_ram[2] # !inst14 & (datain)) # !G1L6 & H1_ram[2];


--H1L44 is RAM_MN_dual2:inst6|ram[15]~973
H1L44 = G1L4 & (inst14 & H1_ram[15] # !inst14 & (datain)) # !G1L4 & H1_ram[15];


--H1L24 is RAM_MN_dual2:inst6|ram[5]~974
H1L24 = G1L13 & (inst14 & H1_ram[5] # !inst14 & (datain)) # !G1L13 & H1_ram[5];


--H1L40 is RAM_MN_dual2:inst6|ram[13]~975
H1L40 = G1L2 & (inst14 & H1_ram[13] # !inst14 & (datain)) # !G1L2 & H1_ram[13];


--H1L28 is RAM_MN_dual2:inst6|ram[7]~976
H1L28 = G1L16 & (inst14 & H1_ram[7] # !inst14 & (datain)) # !G1L16 & H1_ram[7];


--L1L1 is jie_RAM_MN_dual2:inst10|Decoder~321
L1L1 = !K1_seq_addr[2] & !K1_seq_addr[3] & C1_series_addr[0] & K1_seq_addr[1];


--L1L38 is jie_RAM_MN_dual2:inst10|ram[4]~1601
L1L38 = inst14 & (L1L1 & E1L1 # !L1L1 & (L1_ram[4])) # !inst14 & (L1_ram[4]);


--L1L2 is jie_RAM_MN_dual2:inst10|Decoder~322
L1L2 = !K1_seq_addr[2] & K1_seq_addr[3] & !C1_series_addr[0] & K1_seq_addr[1];