interlace.map.eqn

一个简单的交织实现程序

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--G1_dout is RAM_MN_dual:inst5|dout
G1_dout = DFFEAS(G1L27, clk,  ,  ,  ,  ,  , inst14,  );


--H1_dout is RAM_MN_dual2:inst6|dout
H1_dout = DFFEAS(H1L11, clk,  ,  ,  ,  ,  , !inst14,  );


--E1L1 is cobination:inst12|d1d2~10
E1L1 = G1_dout $ H1_dout;


--L1_dout is jie_RAM_MN_dual2:inst10|dout
L1_dout = DFFEAS(L1L27, clk,  ,  ,  ,  ,  , inst14,  );


--D1_dout is jie_RAM_MN_dual:inst2|dout
D1_dout = DFFEAS(D1L11, clk,  ,  ,  ,  ,  , !inst14,  );


--E2L1 is cobination:inst3|d1d2~10
E2L1 = L1_dout $ D1_dout;


--inst14 is inst14
inst14 = DFFEAS(J1L1, clk,  ,  ,  ,  ,  ,  ,  );


--C1_series_addr[3] is jie_counter:inst1|series_addr[3]
C1_series_addr[3] = DFFEAS(C1L31, clk,  ,  ,  ,  ,  ,  ,  );


--C1_series_addr[2] is jie_counter:inst1|series_addr[2]
C1_series_addr[2] = DFFEAS(C1L29, clk,  ,  ,  ,  ,  ,  ,  );


--C1_series_addr[1] is jie_counter:inst1|series_addr[1]
C1_series_addr[1] = DFFEAS(C1L1, clk,  ,  ,  ,  ,  ,  ,  );


--C1_series_addr[0] is jie_counter:inst1|series_addr[0]
C1_series_addr[0] = DFFEAS(C1L26, clk,  ,  ,  ,  ,  ,  ,  );


--K1_seq_addr[3] is rom_mn_seq:inst9|seq_addr[3]
K1_seq_addr[3] = DFFEAS(C1_series_addr[3], clk,  ,  ,  ,  ,  ,  ,  );


--K1_seq_addr[2] is rom_mn_seq:inst9|seq_addr[2]
K1_seq_addr[2] = DFFEAS(C1_series_addr[2], clk,  ,  ,  ,  ,  ,  ,  );


--K1_seq_addr[1] is rom_mn_seq:inst9|seq_addr[1]
K1_seq_addr[1] = DFFEAS(C1_series_addr[1], clk,  ,  ,  ,  ,  ,  ,  );


--G1_ram[14] is RAM_MN_dual:inst5|ram[14]
G1_ram[14] = DFFEAS(G1L58, clk,  ,  ,  ,  ,  ,  ,  );


--G1_ram[13] is RAM_MN_dual:inst5|ram[13]
G1_ram[13] = DFFEAS(G1L56, clk,  ,  ,  ,  ,  ,  ,  );


--G1_ram[12] is RAM_MN_dual:inst5|ram[12]
G1_ram[12] = DFFEAS(G1L54, clk,  ,  ,  ,  ,  ,  ,  );


--G1L18 is RAM_MN_dual:inst5|Mux~56
G1L18 = K1_seq_addr[3] & (K1_seq_addr[2]) # !K1_seq_addr[3] & (K1_seq_addr[2] & G1_ram[13] # !K1_seq_addr[2] & (G1_ram[12]));


--G1_ram[15] is RAM_MN_dual:inst5|ram[15]
G1_ram[15] = DFFEAS(G1L60, clk,  ,  ,  ,  ,  ,  ,  );


--G1L19 is RAM_MN_dual:inst5|Mux~57
G1L19 = K1_seq_addr[3] & (G1L18 & (G1_ram[15]) # !G1L18 & G1_ram[14]) # !K1_seq_addr[3] & (G1L18);


--G1_ram[1] is RAM_MN_dual:inst5|ram[1]
G1_ram[1] = DFFEAS(G1L32, clk,  ,  ,  ,  ,  ,  ,  );


--G1_ram[2] is RAM_MN_dual:inst5|ram[2]
G1_ram[2] = DFFEAS(G1L34, clk,  ,  ,  ,  ,  ,  ,  );


--G1_ram[0] is RAM_MN_dual:inst5|ram[0]
G1_ram[0] = DFFEAS(G1L30, clk,  ,  ,  ,  ,  ,  ,  );


--G1L20 is RAM_MN_dual:inst5|Mux~58
G1L20 = K1_seq_addr[2] & (K1_seq_addr[3]) # !K1_seq_addr[2] & (K1_seq_addr[3] & G1_ram[2] # !K1_seq_addr[3] & (G1_ram[0]));


--G1_ram[3] is RAM_MN_dual:inst5|ram[3]
G1_ram[3] = DFFEAS(G1L36, clk,  ,  ,  ,  ,  ,  ,  );


--G1L21 is RAM_MN_dual:inst5|Mux~59
G1L21 = K1_seq_addr[2] & (G1L20 & (G1_ram[3]) # !G1L20 & G1_ram[1]) # !K1_seq_addr[2] & (G1L20);


--G1_ram[10] is RAM_MN_dual:inst5|ram[10]
G1_ram[10] = DFFEAS(G1L50, clk,  ,  ,  ,  ,  ,  ,  );


--G1_ram[9] is RAM_MN_dual:inst5|ram[9]
G1_ram[9] = DFFEAS(G1L48, clk,  ,  ,  ,  ,  ,  ,  );


--G1_ram[8] is RAM_MN_dual:inst5|ram[8]
G1_ram[8] = DFFEAS(G1L46, clk,  ,  ,  ,  ,  ,  ,  );


--G1L22 is RAM_MN_dual:inst5|Mux~60
G1L22 = K1_seq_addr[3] & (K1_seq_addr[2]) # !K1_seq_addr[3] & (K1_seq_addr[2] & G1_ram[9] # !K1_seq_addr[2] & (G1_ram[8]));


--G1_ram[11] is RAM_MN_dual:inst5|ram[11]
G1_ram[11] = DFFEAS(G1L52, clk,  ,  ,  ,  ,  ,  ,  );


--G1L23 is RAM_MN_dual:inst5|Mux~61
G1L23 = K1_seq_addr[3] & (G1L22 & (G1_ram[11]) # !G1L22 & G1_ram[10]) # !K1_seq_addr[3] & (G1L22);


--G1L24 is RAM_MN_dual:inst5|Mux~62
G1L24 = C1_series_addr[0] & (K1_seq_addr[1]) # !C1_series_addr[0] & (K1_seq_addr[1] & G1L21 # !K1_seq_addr[1] & (G1L23));


--G1_ram[5] is RAM_MN_dual:inst5|ram[5]
G1_ram[5] = DFFEAS(G1L40, clk,  ,  ,  ,  ,  ,  ,  );


--G1_ram[6] is RAM_MN_dual:inst5|ram[6]
G1_ram[6] = DFFEAS(G1L42, clk,  ,  ,  ,  ,  ,  ,  );


--G1_ram[4] is RAM_MN_dual:inst5|ram[4]
G1_ram[4] = DFFEAS(G1L38, clk,  ,  ,  ,  ,  ,  ,  );


--G1L25 is RAM_MN_dual:inst5|Mux~63
G1L25 = K1_seq_addr[2] & (K1_seq_addr[3]) # !K1_seq_addr[2] & (K1_seq_addr[3] & G1_ram[6] # !K1_seq_addr[3] & (G1_ram[4]));


--G1_ram[7] is RAM_MN_dual:inst5|ram[7]
G1_ram[7] = DFFEAS(G1L44, clk,  ,  ,  ,  ,  ,  ,  );


--G1L26 is RAM_MN_dual:inst5|Mux~64
G1L26 = K1_seq_addr[2] & (G1L25 & (G1_ram[7]) # !G1L25 & G1_ram[5]) # !K1_seq_addr[2] & (G1L25);


--G1L27 is RAM_MN_dual:inst5|Mux~65
G1L27 = C1_series_addr[0] & (G1L24 & (G1L26) # !G1L24 & G1L19) # !C1_series_addr[0] & (G1L24);


--H1_ram[4] is RAM_MN_dual2:inst6|ram[4]
H1_ram[4] = DFFEAS(H1L22, clk,  ,  ,  ,  ,  ,  ,  );


--H1_ram[14] is RAM_MN_dual2:inst6|ram[14]
H1_ram[14] = DFFEAS(H1L42, clk,  ,  ,  ,  ,  ,  ,  );


--H1_ram[12] is RAM_MN_dual2:inst6|ram[12]
H1_ram[12] = DFFEAS(H1L38, clk,  ,  ,  ,  ,  ,  ,  );


--H1L2 is RAM_MN_dual2:inst6|Mux~56
H1L2 = K1_seq_addr[1] & (K1_seq_addr[3]) # !K1_seq_addr[1] & (K1_seq_addr[3] & H1_ram[14] # !K1_seq_addr[3] & (H1_ram[12]));


--H1_ram[6] is RAM_MN_dual2:inst6|ram[6]
H1_ram[6] = DFFEAS(H1L26, clk,  ,  ,  ,  ,  ,  ,  );


--H1L3 is RAM_MN_dual2:inst6|Mux~57
H1L3 = K1_seq_addr[1] & (H1L2 & (H1_ram[6]) # !H1L2 & H1_ram[4]) # !K1_seq_addr[1] & (H1L2);


--H1_ram[1] is RAM_MN_dual2:inst6|ram[1]
H1_ram[1] = DFFEAS(H1L16, clk,  ,  ,  ,  ,  ,  ,  );


--H1_ram[11] is RAM_MN_dual2:inst6|ram[11]
H1_ram[11] = DFFEAS(H1L36, clk,  ,  ,  ,  ,  ,  ,  );


--H1_ram[9] is RAM_MN_dual2:inst6|ram[9]
H1_ram[9] = DFFEAS(H1L32, clk,  ,  ,  ,  ,  ,  ,  );


--H1L4 is RAM_MN_dual2:inst6|Mux~58
H1L4 = K1_seq_addr[1] & (K1_seq_addr[3]) # !K1_seq_addr[1] & (K1_seq_addr[3] & H1_ram[11] # !K1_seq_addr[3] & (H1_ram[9]));


--H1_ram[3] is RAM_MN_dual2:inst6|ram[3]
H1_ram[3] = DFFEAS(H1L20, clk,  ,  ,  ,  ,  ,  ,  );


--H1L5 is RAM_MN_dual2:inst6|Mux~59
H1L5 = K1_seq_addr[1] & (H1L4 & (H1_ram[3]) # !H1L4 & H1_ram[1]) # !K1_seq_addr[1] & (H1L4);


--H1_ram[0] is RAM_MN_dual2:inst6|ram[0]
H1_ram[0] = DFFEAS(H1L14, clk,  ,  ,  ,  ,  ,  ,  );


--H1_ram[10] is RAM_MN_dual2:inst6|ram[10]
H1_ram[10] = DFFEAS(H1L34, clk,  ,  ,  ,  ,  ,  ,  );


--H1_ram[8] is RAM_MN_dual2:inst6|ram[8]
H1_ram[8] = DFFEAS(H1L30, clk,  ,  ,  ,  ,  ,  ,  );


--H1L6 is RAM_MN_dual2:inst6|Mux~60
H1L6 = K1_seq_addr[1] & (K1_seq_addr[3]) # !K1_seq_addr[1] & (K1_seq_addr[3] & H1_ram[10] # !K1_seq_addr[3] & (H1_ram[8]));


--H1_ram[2] is RAM_MN_dual2:inst6|ram[2]
H1_ram[2] = DFFEAS(H1L18, clk,  ,  ,  ,  ,  ,  ,  );


--H1L7 is RAM_MN_dual2:inst6|Mux~61
H1L7 = K1_seq_addr[1] & (H1L6 & (H1_ram[2]) # !H1L6 & H1_ram[0]) # !K1_seq_addr[1] & (H1L6);


--H1L8 is RAM_MN_dual2:inst6|Mux~62
H1L8 = C1_series_addr[0] & (K1_seq_addr[2]) # !C1_series_addr[0] & (K1_seq_addr[2] & H1L5 # !K1_seq_addr[2] & (H1L7));


--H1_ram[15] is RAM_MN_dual2:inst6|ram[15]
H1_ram[15] = DFFEAS(H1L44, clk,  ,  ,  ,  ,  ,  ,  );


--H1_ram[5] is RAM_MN_dual2:inst6|ram[5]
H1_ram[5] = DFFEAS(H1L24, clk,  ,  ,  ,  ,  ,  ,  );


--H1_ram[13] is RAM_MN_dual2:inst6|ram[13]
H1_ram[13] = DFFEAS(H1L40, clk,  ,  ,  ,  ,  ,  ,  );


--H1L9 is RAM_MN_dual2:inst6|Mux~63
H1L9 = K1_seq_addr[3] & (K1_seq_addr[1]) # !K1_seq_addr[3] & (K1_seq_addr[1] & H1_ram[5] # !K1_seq_addr[1] & (H1_ram[13]));


--H1_ram[7] is RAM_MN_dual2:inst6|ram[7]
H1_ram[7] = DFFEAS(H1L28, clk,  ,  ,  ,  ,  ,  ,  );


--H1L10 is RAM_MN_dual2:inst6|Mux~64
H1L10 = K1_seq_addr[3] & (H1L9 & (H1_ram[7]) # !H1L9 & H1_ram[15]) # !K1_seq_addr[3] & (H1L9);


--H1L11 is RAM_MN_dual2:inst6|Mux~65
H1L11 = C1_series_addr[0] & (H1L8 & (H1L10) # !H1L8 & H1L3) # !C1_series_addr[0] & (H1L8);


--L1_ram[4] is jie_RAM_MN_dual2:inst10|ram[4]
L1_ram[4] = DFFEAS(L1L38, clk,  ,  ,  ,  ,  ,  ,  );


--L1_ram[2] is jie_RAM_MN_dual2:inst10|ram[2]
L1_ram[2] = DFFEAS(L1L34, clk,  ,  ,  ,  ,  ,  ,  );


--L1_ram[0] is jie_RAM_MN_dual2:inst10|ram[0]
L1_ram[0] = DFFEAS(L1L30, clk,  ,  ,  ,  ,  ,  ,  );


--L1L18 is jie_RAM_MN_dual2:inst10|Mux~56
L1L18 = K1_seq_addr[2] & (K1_seq_addr[1]) # !K1_seq_addr[2] & (K1_seq_addr[1] & L1_ram[2] # !K1_seq_addr[1] & (L1_ram[0]));


--L1_ram[6] is jie_RAM_MN_dual2:inst10|ram[6]
L1_ram[6] = DFFEAS(L1L42, clk,  ,  ,  ,  ,  ,  ,  );


--L1L19 is jie_RAM_MN_dual2:inst10|Mux~57
L1L19 = K1_seq_addr[2] & (L1L18 & (L1_ram[6]) # !L1L18 & L1_ram[4]) # !K1_seq_addr[2] & (L1L18);


--L1_ram[13] is jie_RAM_MN_dual2:inst10|ram[13]
L1_ram[13] = DFFEAS(L1L56, clk,  ,  ,  ,  ,  ,  ,  );


--L1_ram[11] is jie_RAM_MN_dual2:inst10|ram[11]
L1_ram[11] = DFFEAS(L1L52, clk,  ,  ,  ,  ,  ,  ,  );


--L1_ram[9] is jie_RAM_MN_dual2:inst10|ram[9]
L1_ram[9] = DFFEAS(L1L48, clk,  ,  ,  ,  ,  ,  ,  );


--L1L20 is jie_RAM_MN_dual2:inst10|Mux~58
L1L20 = K1_seq_addr[2] & (K1_seq_addr[1]) # !K1_seq_addr[2] & (K1_seq_addr[1] & L1_ram[11] # !K1_seq_addr[1] & (L1_ram[9]));


--L1_ram[15] is jie_RAM_MN_dual2:inst10|ram[15]
L1_ram[15] = DFFEAS(L1L60, clk,  ,  ,  ,  ,  ,  ,  );


--L1L21 is jie_RAM_MN_dual2:inst10|Mux~59
L1L21 = K1_seq_addr[2] & (L1L20 & (L1_ram[15]) # !L1L20 & L1_ram[13]) # !K1_seq_addr[2] & (L1L20);


--L1_ram[5] is jie_RAM_MN_dual2:inst10|ram[5]
L1_ram[5] = DFFEAS(L1L40, clk,  ,  ,  ,  ,  ,  ,  );


--L1_ram[3] is jie_RAM_MN_dual2:inst10|ram[3]
L1_ram[3] = DFFEAS(L1L36, clk,  ,  ,  ,  ,  ,  ,  );


--L1_ram[1] is jie_RAM_MN_dual2:inst10|ram[1]
L1_ram[1] = DFFEAS(L1L32, clk,  ,  ,  ,  ,  ,  ,  );


--L1L22 is jie_RAM_MN_dual2:inst10|Mux~60
L1L22 = K1_seq_addr[2] & (K1_seq_addr[1]) # !K1_seq_addr[2] & (K1_seq_addr[1] & L1_ram[3] # !K1_seq_addr[1] & (L1_ram[1]));


--L1_ram[7] is jie_RAM_MN_dual2:inst10|ram[7]
L1_ram[7] = DFFEAS(L1L44, clk,  ,  ,  ,  ,  ,  ,  );


--L1L23 is jie_RAM_MN_dual2:inst10|Mux~61
L1L23 = K1_seq_addr[2] & (L1L22 & (L1_ram[7]) # !L1L22 & L1_ram[5]) # !K1_seq_addr[2] & (L1L22);


--L1L24 is jie_RAM_MN_dual2:inst10|Mux~62
L1L24 = C1_series_addr[0] & (K1_seq_addr[3]) # !C1_series_addr[0] & (K1_seq_addr[3] & L1L21 # !K1_seq_addr[3] & (L1L23));


--L1_ram[12] is jie_RAM_MN_dual2:inst10|ram[12]
L1_ram[12] = DFFEAS(L1L54, clk,  ,  ,  ,  ,  ,  ,  );


--L1_ram[10] is jie_RAM_MN_dual2:inst10|ram[10]
L1_ram[10] = DFFEAS(L1L50, clk,  ,  ,  ,  ,  ,  ,  );


--L1_ram[8] is jie_RAM_MN_dual2:inst10|ram[8]
L1_ram[8] = DFFEAS(L1L46, clk,  ,  ,  ,  ,  ,  ,  );


--L1L25 is jie_RAM_MN_dual2:inst10|Mux~63