jie_rom_mn_seq.vhd

一个简单的交织实现程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--  生成一个二维的地址表
entity jie_rom_mn_seq is
 port
   ( counter : in std_logic_vector(3 downto 0);--integer range  0 to 15; --15=m*n-1=4*4-1
     clk     : in std_logic;
     seq_addr: out std_logic_vector(3 downto 0)
   );
 end jie_rom_mn_seq;

architecture beha of jie_rom_mn_seq is
 subtype rom_word is std_logic_vector(3 downto 0);
 type rom_table is array (0 to 15) of rom_word; --15=m*n-1
constant rom: rom_table:= rom_table'(  --4*4
---1
rom_word'("1100"),   -- the high 4 bits is row ,the low 4 bits is colum
rom_word'("1000"),
rom_word'("0100"),
rom_word'("0000"),
rom_word'("1101"), --13
rom_word'("1001"),
rom_word'("0101"),
rom_word'("0001"),
rom_word'("1110"),
rom_word'("1010"),
rom_word'("0110"),
rom_word'("0010"),
rom_word'("1111"), 
rom_word'("1011"),
rom_word'("0111"),
rom_word'("0011")

    );

begin
process(clk)
 begin
  if (clk'event and clk='1' ) then 
    
    seq_addr<=rom(conv_integer(counter));
     
 end if;
end process;
end beha;