jiaozhijiejiaozhi.sim.rpt

一个简单的交织实现程序

Memory report data cannot be output to ASCII.
Please use Quartus II to view the memory report data.


+---------------------------------------------------------------------------------------------------------------------+
; |jiaozhijiejiaozhi|interlace:inst|RAM_MN_dual2:inst6|altsyncram:ram_rtl_2|altsyncram_1qe1:auto_generated|ALTSYNCRAM ;
+---------------------------------------------------------------------------------------------------------------------+
Memory report data cannot be output to ASCII.
Please use Quartus II to view the memory report data.


+--------------------------------------------------------------------------------------------------------------------+
; |jiaozhijiejiaozhi|interlace:inst|RAM_MN_dual:inst2|altsyncram:ram_rtl_3|altsyncram_1qe1:auto_generated|ALTSYNCRAM ;
+--------------------------------------------------------------------------------------------------------------------+
Memory report data cannot be output to ASCII.
Please use Quartus II to view the memory report data.


+--------------------------------------------------------------------+
; Coverage Summary                                                   ;
+-----------------------------------------------------+--------------+
; Type                                                ; Value        ;
+-----------------------------------------------------+--------------+
; Total coverage as a percentage                      ;      95.65 % ;
; Total nodes checked                                 ; 104          ;
; Total output ports checked                          ; 115          ;
; Total output ports with complete 1/0-value coverage ; 110          ;
; Total output ports with no 1/0-value coverage       ; 1            ;
; Total output ports with no 1-value coverage         ; 1            ;
; Total output ports with no 0-value coverage         ; 5            ;
+-----------------------------------------------------+--------------+


The following table displays output ports that toggle between 1 and 0 during simulation.
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage                                                                                                                                                                                                                                  ;
+---------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------+------------------+
; Node Name                                                                                                           ; Output Port Name                                                                                                    ; Output Port Type ;
+---------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------+------------------+
; |jiaozhijiejiaozhi|jieinterlace:inst1|RAM_MN_dual2:inst6|dout                                                       ; |jiaozhijiejiaozhi|jieinterlace:inst1|RAM_MN_dual2:inst6|dout                                                       ; regout           ;
; |jiaozhijiejiaozhi|jieinterlace:inst1|RAM_MN_dual:inst5|dout                                                        ; |jiaozhijiejiaozhi|jieinterlace:inst1|RAM_MN_dual:inst5|dout                                                        ; regout           ;
; |jiaozhijiejiaozhi|jieinterlace:inst1|cobination:inst12|Add0~10                                                     ; |jiaozhijiejiaozhi|jieinterlace:inst1|cobination:inst12|Add0~10                                                     ; combout          ;
; |jiaozhijiejiaozhi|interlace:inst|RAM_MN_dual2:inst6|dout                                                           ; |jiaozhijiejiaozhi|interlace:inst|RAM_MN_dual2:inst6|dout                                                           ; regout           ;
; |jiaozhijiejiaozhi|interlace:inst|RAM_MN_dual:inst2|dout                                                            ; |jiaozhijiejiaozhi|interlace:inst|RAM_MN_dual:inst2|dout                                                            ; regout           ;
; |jiaozhijiejiaozhi|interlace:inst|cobination:inst3|Add0~10                                                          ; |jiaozhijiejiaozhi|interlace:inst|cobination:inst3|Add0~10                                                          ; combout          ;
; |jiaozhijiejiaozhi|interlace:inst|source:inst1|dataout                                                              ; |jiaozhijiejiaozhi|interlace:inst|source:inst1|dataout                                                              ; regout           ;
; |jiaozhijiejiaozhi|interlace:inst|inst8                                                                             ; |jiaozhijiejiaozhi|interlace:inst|inst8                                                                             ; regout           ;
; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|series_addr1[4]                                                ; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|series_addr1[4]                                                ; regout           ;
; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|series_addr1[3]                                                ; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|series_addr1[3]                                                ; regout           ;
; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|series_addr1[2]                                                ; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|series_addr1[2]                                                ; regout           ;
; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|series_addr1[1]                                                ; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|series_addr1[1]                                                ; regout           ;
; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|series_addr1[0]                                                ; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|series_addr1[0]                                                ; regout           ;
; |jiaozhijiejiaozhi|jieinterlace:inst1|RAM_MN_dual2:inst6|altsyncram:ram_rtl_0|altsyncram_1qe1:auto_generated|q_b[0] ; |jiaozhijiejiaozhi|jieinterlace:inst1|RAM_MN_dual2:inst6|altsyncram:ram_rtl_0|altsyncram_1qe1:auto_generated|q_b[0] ; portbdataout0    ;
; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|cnt[5]                                                         ; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|cnt[5]                                                         ; regout           ;
; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|cnt[2]                                                         ; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|cnt[2]                                                         ; regout           ;
; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|cnt[1]                                                         ; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|cnt[1]                                                         ; regout           ;
; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|cnt[4]                                                         ; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|cnt[4]                                                         ; regout           ;
; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|cnt[3]                                                         ; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|cnt[3]                                                         ; regout           ;
; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|LessThan0~48                                                   ; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|LessThan0~48                                                   ; combout          ;
; |jiaozhijiejiaozhi|jieinterlace:inst1|RAM_MN_dual2:inst6|dout~29                                                    ; |jiaozhijiejiaozhi|jieinterlace:inst1|RAM_MN_dual2:inst6|dout~29                                                    ; combout          ;
; |jiaozhijiejiaozhi|jieinterlace:inst1|RAM_MN_dual:inst5|altsyncram:ram_rtl_1|altsyncram_1qe1:auto_generated|q_b[0]  ; |jiaozhijiejiaozhi|jieinterlace:inst1|RAM_MN_dual:inst5|altsyncram:ram_rtl_1|altsyncram_1qe1:auto_generated|q_b[0]  ; portbdataout0    ;
; |jiaozhijiejiaozhi|jieinterlace:inst1|RAM_MN_dual:inst5|dout~25                                                     ; |jiaozhijiejiaozhi|jieinterlace:inst1|RAM_MN_dual:inst5|dout~25                                                     ; combout          ;
; |jiaozhijiejiaozhi|interlace:inst|RAM_MN_dual2:inst6|altsyncram:ram_rtl_2|altsyncram_1qe1:auto_generated|q_b[0]     ; |jiaozhijiejiaozhi|interlace:inst|RAM_MN_dual2:inst6|altsyncram:ram_rtl_2|altsyncram_1qe1:auto_generated|q_b[0]     ; portbdataout0    ;
; |jiaozhijiejiaozhi|interlace:inst|RAM_MN_dual2:inst6|dout~29                                                        ; |jiaozhijiejiaozhi|interlace:inst|RAM_MN_dual2:inst6|dout~29                                                        ; combout          ;
; |jiaozhijiejiaozhi|interlace:inst|RAM_MN_dual:inst2|altsyncram:ram_rtl_3|altsyncram_1qe1:auto_generated|q_b[0]      ; |jiaozhijiejiaozhi|interlace:inst|RAM_MN_dual:inst2|altsyncram:ram_rtl_3|altsyncram_1qe1:auto_generated|q_b[0]      ; portbdataout0    ;
; |jiaozhijiejiaozhi|interlace:inst|RAM_MN_dual:inst2|dout~25                                                         ; |jiaozhijiejiaozhi|interlace:inst|RAM_MN_dual:inst2|dout~25                                                         ; combout          ;
; |jiaozhijiejiaozhi|interlace:inst|rom_mn_seq:inst9|seq_addr[0]                                                      ; |jiaozhijiejiaozhi|interlace:inst|rom_mn_seq:inst9|seq_addr[0]                                                      ; regout           ;
; |jiaozhijiejiaozhi|interlace:inst|source:inst1|m[2]                                                                 ; |jiaozhijiejiaozhi|interlace:inst|source:inst1|m[2]                                                                 ; regout           ;
; |jiaozhijiejiaozhi|interlace:inst|source:inst1|m[3]                                                                 ; |jiaozhijiejiaozhi|interlace:inst|source:inst1|m[3]                                                                 ; regout           ;
; |jiaozhijiejiaozhi|interlace:inst|source:inst1|Mux0~23                                                              ; |jiaozhijiejiaozhi|interlace:inst|source:inst1|Mux0~23                                                              ; combout          ;
; |jiaozhijiejiaozhi|interlace:inst|RAM_MN_dual:inst2|flag1                                                           ; |jiaozhijiejiaozhi|interlace:inst|RAM_MN_dual:inst2|flag1                                                           ; regout           ;
; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|Add0~76                                                        ; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|Add0~76                                                        ; sumout           ;
; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|Add0~76                                                        ; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|Add0~77                                                        ; cout             ;
; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|Add0~80                                                        ; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|Add0~80                                                        ; sumout           ;
; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|Add0~80                                                        ; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|Add0~81                                                        ; cout             ;
; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|Add0~84                                                        ; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|Add0~84                                                        ; sumout           ;
; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|Add0~84                                                        ; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|Add0~85                                                        ; cout             ;
; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|Add0~88                                                        ; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|Add0~88                                                        ; sumout           ;
; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|Add0~88                                                        ; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|Add0~89                                                        ; cout             ;
; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|Add0~92                                                        ; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|Add0~92                                                        ; sumout           ;
; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|series_addr1[4]~83                                             ; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|series_addr1[4]~83                                             ; combout          ;
; |jiaozhijiejiaozhi|jieinterlace:inst1|rom_mn_seq:inst2|seq_addr[0]                                                  ; |jiaozhijiejiaozhi|jieinterlace:inst1|rom_mn_seq:inst2|seq_addr[0]                                                  ; regout           ;
; |jiaozhijiejiaozhi|jieinterlace:inst1|rom_mn_seq:inst2|seq_addr[1]                                                  ; |jiaozhijiejiaozhi|jieinterlace:inst1|rom_mn_seq:inst2|seq_addr[1]                                                  ; regout           ;
; |jiaozhijiejiaozhi|jieinterlace:inst1|rom_mn_seq:inst2|seq_addr[2]                                                  ; |jiaozhijiejiaozhi|jieinterlace:inst1|rom_mn_seq:inst2|seq_addr[2]                                                  ; regout           ;
; |jiaozhijiejiaozhi|jieinterlace:inst1|rom_mn_seq:inst2|seq_addr[3]                                                  ; |jiaozhijiejiaozhi|jieinterlace:inst1|rom_mn_seq:inst2|seq_addr[3]                                                  ; regout           ;
; |jiaozhijiejiaozhi|jieinterlace:inst1|rom_mn_seq:inst2|seq_addr[4]                                                  ; |jiaozhijiejiaozhi|jieinterlace:inst1|rom_mn_seq:inst2|seq_addr[4]                                                  ; regout           ;
; |jiaozhijiejiaozhi|jieinterlace:inst1|rom_mn_interlace:inst|Mux3~358                                                ; |jiaozhijiejiaozhi|jieinterlace:inst1|rom_mn_interlace:inst|Mux3~358                                                ; combout          ;
; |jiaozhijiejiaozhi|jieinterlace:inst1|rom_mn_interlace:inst|Mux2~66                                                 ; |jiaozhijiejiaozhi|jieinterlace:inst1|rom_mn_interlace:inst|Mux2~66                                                 ; combout          ;
; |jiaozhijiejiaozhi|jieinterlace:inst1|rom_mn_interlace:inst|Mux1~65                                                 ; |jiaozhijiejiaozhi|jieinterlace:inst1|rom_mn_interlace:inst|Mux1~65                                                 ; combout          ;
; |jiaozhijiejiaozhi|jieinterlace:inst1|rom_mn_interlace:inst|Mux0~59                                                 ; |jiaozhijiejiaozhi|jieinterlace:inst1|rom_mn_interlace:inst|Mux0~59                                                 ; combout          ;
; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|Add1~91                                                        ; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|Add1~91                                                        ; sumout           ;
; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|Add1~91                                                        ; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|Add1~92                                                        ; cout             ;
; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|Add1~95                                                        ; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|Add1~95                                                        ; sumout           ;
; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|Add1~95                                                        ; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|Add1~96                                                        ; cout             ;
; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|Add1~99                                                        ; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|Add1~99                                                        ; sumout           ;
; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|Add1~99                                                        ; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|Add1~100                                                       ; cout             ;
; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|Add1~103                                                       ; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|Add1~103                                                       ; sumout           ;
; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|Add1~103                                                       ; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|Add1~104                                                       ; cout             ;
; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|Add1~107                                                       ; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|Add1~107                                                       ; sumout           ;
; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|Equal1~32                                                      ; |jiaozhijiejiaozhi|jieinterlace:inst1|counter2:inst1|Equal1~32                                                      ; combout          ;
; |jiaozhijiejiaozhi|interlace:inst|rom_mn_seq:inst9|seq_addr[1]                                                      ; |jiaozhijiejiaozhi|interlace:inst|rom_mn_seq:inst9|seq_addr[1]                                                      ; regout           ;
; |jiaozhijiejiaozhi|interlace:inst|rom_mn_seq:inst9|seq_addr[2]                                                      ; |jiaozhijiejiaozhi|interlace:inst|rom_mn_seq:inst9|seq_addr[2]                                                      ; regout           ;
; |jiaozhijiejiaozhi|interlace:inst|rom_mn_seq:inst9|seq_addr[3]                                                      ; |jiaozhijiejiaozhi|interlace:inst|rom_mn_seq:inst9|seq_addr[3]                                                      ; regout           ;