interlace.map.summary

来自「一个简单的交织实现程序」· SUMMARY 代码 · 共 14 行

Analysis & Synthesis Status : Successful - Mon Apr 07 22:22:09 2008
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : interlace
Top-level Entity Name : interlace
Family : Stratix II
Total ALUTs : 36
Total registers : 32
Total pins : 21
Total virtual pins : 0
Total memory bits : 64
DSP block 9-bit elements : 0
Total PLLs : 0
Total DLLs : 0