jieinterlace.map.summary

来自「一个简单的交织实现程序」· SUMMARY 代码 · 共 14 行

Analysis & Synthesis Status : Successful - Tue Apr 08 21:18:59 2008
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : jieinterlace
Top-level Entity Name : jiaozhijiejiaozhi
Family : Stratix II
Total ALUTs : 38
Total registers : 35
Total pins : 7
Total virtual pins : 0
Total memory bits : 128
DSP block 9-bit elements : 0
Total PLLs : 0
Total DLLs : 0