jieinterlace.tan.rpt
来自「一个简单的交织实现程序」· RPT 代码 · 共 211 行 · 第 1/5 页
RPT
211 行
; N/A ; 486.85 MHz ( period = 2.054 ns ) ; interlace:inst|counter:inst8|series_addr[0] ; jieinterlace:inst2|RAM_MN_dual:inst5|altsyncram:ram_rtl_1|altsyncram_tmi1:auto_generated|ram_block1a0~portb_address_reg3 ; clk ; clk ; None ; None ; 1.773 ns ;
; N/A ; 487.09 MHz ( period = 2.053 ns ) ; jieinterlace:inst2|RAM_MN_dual2:inst6|Mux0~54 ; interlace:inst|RAM_MN_dual:inst5|dout ; clk ; clk ; None ; None ; 1.869 ns ;
; N/A ; 487.09 MHz ( period = 2.053 ns ) ; jieinterlace:inst2|RAM_MN_dual2:inst6|Mux0~54 ; interlace:inst|RAM_MN_dual2:inst6|dout ; clk ; clk ; None ; None ; 1.869 ns ;
; N/A ; 491.40 MHz ( period = 2.035 ns ) ; interlace:inst|counter:inst8|cnt[1] ; jieinterlace:inst2|RAM_MN_dual:inst5|altsyncram:ram_rtl_1|altsyncram_tmi1:auto_generated|ram_block1a0~porta_we_reg ; clk ; clk ; None ; None ; 1.768 ns ;
; N/A ; 492.13 MHz ( period = 2.032 ns ) ; interlace:inst|counter:inst8|series_addr[1] ; jieinterlace:inst2|RAM_MN_dual:inst5|altsyncram:ram_rtl_1|altsyncram_tmi1:auto_generated|ram_block1a0~portb_address_reg3 ; clk ; clk ; None ; None ; 1.751 ns ;
; N/A ; 493.58 MHz ( period = 2.026 ns ) ; interlace:inst|counter:inst8|series_addr[2] ; jieinterlace:inst2|RAM_MN_dual2:inst6|altsyncram:ram_rtl_0|altsyncram_tmi1:auto_generated|ram_block1a0~portb_address_reg4 ; clk ; clk ; None ; None ; 1.746 ns ;
; N/A ; 495.05 MHz ( period = 2.020 ns ) ; jieinterlace:inst2|RAM_MN_dual2:inst6|Mux0~55 ; interlace:inst|RAM_MN_dual:inst5|dout ; clk ; clk ; None ; None ; 1.837 ns ;
; N/A ; 495.05 MHz ( period = 2.020 ns ) ; jieinterlace:inst2|RAM_MN_dual2:inst6|Mux0~55 ; interlace:inst|RAM_MN_dual2:inst6|dout ; clk ; clk ; None ; None ; 1.837 ns ;
; N/A ; 499.50 MHz ( period = 2.002 ns ) ; interlace:inst|counter:inst8|series_addr[2] ; jieinterlace:inst2|RAM_MN_dual2:inst6|altsyncram:ram_rtl_0|altsyncram_tmi1:auto_generated|ram_block1a0~portb_address_reg1 ; clk ; clk ; None ; None ; 1.722 ns ;
; N/A ; 499.50 MHz ( period = 2.002 ns ) ; interlace:inst|counter:inst8|series_addr[2] ; jieinterlace:inst2|RAM_MN_dual2:inst6|altsyncram:ram_rtl_0|altsyncram_tmi1:auto_generated|ram_block1a0~portb_address_reg2 ; clk ; clk ; None ; None ; 1.722 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; interlace:inst|counter:inst8|series_addr[2] ; jieinterlace:inst2|RAM_MN_dual2:inst6|altsyncram:ram_rtl_0|altsyncram_tmi1:auto_generated|ram_block1a0~portb_address_reg3 ; clk ; clk ; None ; None ; 1.717 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; interlace:inst|counter:inst8|series_addr[0] ; jieinterlace:inst2|RAM_MN_dual2:inst6|altsyncram:ram_rtl_0|altsyncram_tmi1:auto_generated|ram_block1a0~portb_address_reg4 ; clk ; clk ; None ; None ; 1.706 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; interlace:inst|counter:inst8|cnt[2] ; interlace:inst|counter:inst8|cnt[4] ; clk ; clk ; None ; None ; 1.800 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; interlace:inst|counter:inst8|cnt[2] ; interlace:inst|counter:inst8|cnt[5] ; clk ; clk ; None ; None ; 1.800 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; interlace:inst|counter:inst8|cnt[2] ; interlace:inst|counter:inst8|cnt[3] ; clk ; clk ; None ; None ; 1.800 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; interlace:inst|counter:inst8|cnt[2] ; interlace:inst|counter:inst8|cnt[2] ; clk ; clk ; None ; None ; 1.800 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; interlace:inst|counter:inst8|cnt[5] ; jieinterlace:inst2|RAM_MN_dual2:inst6|altsyncram:ram_rtl_0|altsyncram_tmi1:auto_generated|ram_block1a0~porta_we_reg ; clk ; clk ; None ; None ; 1.704 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; interlace:inst|counter:inst8|cnt[2] ; interlace:inst|RAM_MN_dual:inst5|dout ; clk ; clk ; None ; None ; 1.780 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; interlace:inst|counter:inst8|cnt[2] ; jieinterlace:inst2|RAM_MN_dual:inst5|dout ; clk ; clk ; None ; None ; 1.775 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; interlace:inst|counter:inst8|series_addr[3] ; jieinterlace:inst2|RAM_MN_dual2:inst6|altsyncram:ram_rtl_0|altsyncram_tmi1:auto_generated|ram_block1a0~portb_address_reg4 ; clk ; clk ; None ; None ; 1.659 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; interlace:inst|counter:inst8|cnt[5] ; jieinterlace:inst2|RAM_MN_dual2:inst6|Mux0~45 ; clk ; clk ; None ; None ; 1.753 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; interlace:inst|counter:inst8|series_addr[4] ; jieinterlace:inst2|RAM_MN_dual2:inst6|altsyncram:ram_rtl_0|altsyncram_tmi1:auto_generated|ram_block1a0~portb_address_reg4 ; clk ; clk ; None ; None ; 1.641 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; interlace:inst|counter:inst8|series_addr[3] ; jieinterlace:inst2|RAM_MN_dual2:inst6|altsyncram:ram_rtl_0|altsyncram_tmi1:auto_generated|ram_block1a0~portb_address_reg3 ; clk ; clk ; None ; None ; 1.629 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; interlace:inst|counter:inst8|cnt[2] ; interlace:inst|RAM_MN_dual2:inst6|dout ; clk ; clk ; None ; None ; 1.718 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; interlace:inst|counter:inst8|cnt[2] ; jieinterlace:inst2|RAM_MN_dual2:inst6|dout ; clk ; clk ; None ; None ; 1.714 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; interlace:inst|counter:inst8|series_addr[4] ; jieinterlace:inst2|RAM_MN_dual2:inst6|altsyncram:ram_rtl_0|altsyncram_tmi1:auto_generated|ram_block1a0~portb_address_reg2 ; clk ; clk ; None ; None ; 1.611 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; interlace:inst|counter:inst8|series_addr[4] ; jieinterlace:inst2|RAM_MN_dual2:inst6|altsyncram:ram_rtl_0|altsyncram_tmi1:auto_generated|ram_block1a0~portb_address_reg3 ; clk ; clk ; None ; None ; 1.611 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; interlace:inst|counter:inst8|series_addr[3] ; jieinterlace:inst2|RAM_MN_dual2:inst6|altsyncram:ram_rtl_0|altsyncram_tmi1:auto_generated|ram_block1a0~portb_address_reg1 ; clk ; clk ; None ; None ; 1.605 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; interlace:inst|counter:inst8|cnt[4] ; jieinterlace:inst2|RAM_MN_dual2:inst6|altsyncram:ram_rtl_0|altsyncram_tmi1:auto_generated|ram_block1a0~porta_we_reg ; clk ; clk ; None ; None ; 1.601 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; jieinterlace:inst2|RAM_MN_dual2:inst6|Mux0~61 ; jieinterlace:inst2|RAM_MN_dual2:inst6|dout ; clk ; clk ; None ; None ; 1.669 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; jieinterlace:inst2|RAM_MN_dual2:inst6|Mux0~61 ; jieinterlace:inst2|RAM_MN_dual:inst5|dout ; clk ; clk ; None ; None ; 1.669 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; interlace:inst|counter:inst8|series_addr[4] ; jieinterlace:inst2|RAM_MN_dual2:inst6|altsyncram:ram_rtl_0|altsyncram_tmi1:auto_generated|ram_block1a0~portb_address_reg1 ; clk ; clk ; None ; None ; 1.571 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; interlace:inst|counter:inst8|series_addr[3] ; jieinterlace:inst2|RAM_MN_dual2:inst6|altsyncram:ram_rtl_0|altsyncram_tmi1:auto_generated|ram_block1a0~portb_address_reg2 ; clk ; clk ; None ; None ; 1.568 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; interlace:inst|counter:inst8|series_addr[0] ; jieinterlace:inst2|RAM_MN_dual:inst5|altsyncram:ram_rtl_1|altsyncram_tmi1:auto_generated|ram_block1a0~portb_address_reg2 ; clk ; clk ; None ; None ; 1.562 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; interlace:inst|counter:inst8|cnt[4] ; jieinterlace:inst2|RAM_MN_dual2:inst6|Mux0~45 ; clk ; clk ; None ; None ; 1.650 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; interlace:inst|counter:inst8|cnt[3] ; jieinterlace:inst2|RAM_MN_dual2:inst6|altsyncram:ram_rtl_0|altsyncram_tmi1:auto_generated|ram_block1a0~porta_we_reg ; clk ; clk ; None ; None ; 1.568 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; jieinterlace:inst2|RAM_MN_dual2:inst6|Mux0~52 ; jieinterlace:inst2|RAM_MN_dual2:inst6|dout ; clk ; clk ; None ; None ; 1.649 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; jieinterlace:inst2|RAM_MN_dual2:inst6|Mux0~52 ; jieinterlace:inst2|RAM_MN_dual:inst5|dout ; clk ; clk ; None ; None ; 1.649 ns ;
; N/A ⌨️ 快捷键说明
复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?