counter1.v

来自「一个简单的交织实现程序」· Verilog 代码 · 共 26 行

module counter1(clk,series_addr,ch );
  input    clk;
  output  [4:0] series_addr;
  reg     [4:0] series_addr;


  output reg ch;
  reg [5:0] cnt;
parameter NN=30; //m= 5,n=6 ;NN=m*n
always @(posedge clk  )
    if (series_addr==NN-1  )
         series_addr<=5'b0;            
 	else  
	    series_addr<=series_addr+5'b1;      
           
always @(posedge clk  )
    if (cnt==2*NN-1  )
       cnt<=5'b0;            
 	else  
	   cnt<=cnt+5'b1;      
       
always @(cnt)
  if (cnt<=NN-1) 
      ch<=1'b1;
   else ch<=1'b0;
 endmodule