ram_mn_dual2.vhd

来自「一个简单的交织实现程序」· VHDL 代码 · 共 37 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity RAM_MN_dual2 is --dual ports ram ,read and write at the same time .
 port
   (   wr_addr :in std_logic_vector(4 downto 0);  --write address bus  --integer range  0 to 155; --155=m*n-1=13*12-1
       re_addr :in std_logic_vector(4 downto 0);  --read 
    	 CLK  :in std_logic;                    --wr
		 CH : IN std_logic;  -- SELECT signal port
       din  :in  std_logic;   --read data bus
	   dout :out std_logic    --read data bus
      -- wr_en:in std_logic :='0';      --write enable port
       --re_en:in std_logic :='0'       --read  enable port
    
   );
 end RAM_MN_dual2;

architecture beha of RAM_MN_dual2 is
 subtype ram_word is std_logic ;  
 type ram_table is array (0 to 29) of ram_word; --255=16x16-1
 signal ram: ram_table;
-- signal wr_en,re_en:std_logic;
begin 
process(CLK)
 	begin
    if CLK'event and CLK='0' then
        if ch='0' then
		    ram(conv_integer(wr_addr))<=din;
		    dout <= '0'; --06.10.25
		else
		    dout<=ram(conv_integer(re_addr))  ;
		end if;
	end if;
end process;	
 
end beha;