counter2.tan.qmsg

一个简单的交织实现程序

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register cnt\[2\] cnt\[4\] 500.0 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 500.0 MHz between source register \"cnt\[2\]\" and destination register \"cnt\[4\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.0 ns " "Info: fmax restricted to clock pin edge rate 2.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.305 ns + Longest register register " "Info: + Longest register to register delay is 1.305 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt\[2\] 1 REG LCFF_X1_Y16_N25 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y16_N25; Fanout = 7; REG Node = 'cnt\[2\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { cnt[2] } "NODE_NAME" } } { "counter2.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/counter2/counter2.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.309 ns) + CELL(0.309 ns) 0.618 ns Add1~100 2 COMB LCCOMB_X1_Y16_N4 2 " "Info: 2: + IC(0.309 ns) + CELL(0.309 ns) = 0.618 ns; Loc. = LCCOMB_X1_Y16_N4; Fanout = 2; COMB Node = 'Add1~100'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.618 ns" { cnt[2] Add1~100 } "NODE_NAME" } } { "counter2.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/counter2/counter2.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.035 ns) 0.653 ns Add1~104 3 COMB LCCOMB_X1_Y16_N6 2 " "Info: 3: + IC(0.000 ns) + CELL(0.035 ns) = 0.653 ns; Loc. = LCCOMB_X1_Y16_N6; Fanout = 2; COMB Node = 'Add1~104'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.035 ns" { Add1~100 Add1~104 } "NODE_NAME" } } { "counter2.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/counter2/counter2.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.125 ns) 0.778 ns Add1~107 4 COMB LCCOMB_X1_Y16_N8 1 " "Info: 4: + IC(0.000 ns) + CELL(0.125 ns) = 0.778 ns; Loc. = LCCOMB_X1_Y16_N8; Fanout = 1; COMB Node = 'Add1~107'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.125 ns" { Add1~104 Add1~107 } "NODE_NAME" } } { "counter2.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/counter2/counter2.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.319 ns) + CELL(0.053 ns) 1.150 ns cnt~161 5 COMB LCCOMB_X1_Y16_N22 1 " "Info: 5: + IC(0.319 ns) + CELL(0.053 ns) = 1.150 ns; Loc. = LCCOMB_X1_Y16_N22; Fanout = 1; COMB Node = 'cnt~161'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.372 ns" { Add1~107 cnt~161 } "NODE_NAME" } } { "counter2.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/counter2/counter2.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 1.305 ns cnt\[4\] 6 REG LCFF_X1_Y16_N23 3 " "Info: 6: + IC(0.000 ns) + CELL(0.155 ns) = 1.305 ns; Loc. = LCFF_X1_Y16_N23; Fanout = 3; REG Node = 'cnt\[4\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.155 ns" { cnt~161 cnt[4] } "NODE_NAME" } } { "counter2.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/counter2/counter2.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.677 ns ( 51.88 % ) " "Info: Total cell delay = 0.677 ns ( 51.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.628 ns ( 48.12 % ) " "Info: Total interconnect delay = 0.628 ns ( 48.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.305 ns" { cnt[2] Add1~100 Add1~104 Add1~107 cnt~161 cnt[4] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "1.305 ns" { cnt[2] Add1~100 Add1~104 Add1~107 cnt~161 cnt[4] } { 0.000ns 0.309ns 0.000ns 0.000ns 0.319ns 0.000ns } { 0.000ns 0.309ns 0.035ns 0.125ns 0.053ns 0.155ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.920 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.920 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.844 ns) 0.844 ns clk 1 CLK PIN_P23 1 " "Info: 1: + IC(0.000 ns) + CELL(0.844 ns) = 0.844 ns; Loc. = PIN_P23; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "counter2.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/counter2/counter2.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.187 ns clk~clkctrl 2 COMB CLKCTRL_G3 11 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.187 ns; Loc. = CLKCTRL_G3; Fanout = 11; COMB Node = 'clk~clkctrl'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "counter2.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/counter2/counter2.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.115 ns) + CELL(0.618 ns) 2.920 ns cnt\[4\] 3 REG LCFF_X1_Y16_N23 3 " "Info: 3: + IC(1.115 ns) + CELL(0.618 ns) = 2.920 ns; Loc. = LCFF_X1_Y16_N23; Fanout = 3; REG Node = 'cnt\[4\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.733 ns" { clk~clkctrl cnt[4] } "NODE_NAME" } } { "counter2.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/counter2/counter2.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.462 ns ( 50.07 % ) " "Info: Total cell delay = 1.462 ns ( 50.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.458 ns ( 49.93 % ) " "Info: Total interconnect delay = 1.458 ns ( 49.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.920 ns" { clk clk~clkctrl cnt[4] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.920 ns" { clk clk~combout clk~clkctrl cnt[4] } { 0.000ns 0.000ns 0.343ns 1.115ns } { 0.000ns 0.844ns 0.000ns 0.618ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.920 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.920 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.844 ns) 0.844 ns clk 1 CLK PIN_P23 1 " "Info: 1: + IC(0.000 ns) + CELL(0.844 ns) = 0.844 ns; Loc. = PIN_P23; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "counter2.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/counter2/counter2.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.187 ns clk~clkctrl 2 COMB CLKCTRL_G3 11 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.187 ns; Loc. = CLKCTRL_G3; Fanout = 11; COMB Node = 'clk~clkctrl'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "counter2.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/counter2/counter2.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.115 ns) + CELL(0.618 ns) 2.920 ns cnt\[2\] 3 REG LCFF_X1_Y16_N25 7 " "Info: 3: + IC(1.115 ns) + CELL(0.618 ns) = 2.920 ns; Loc. = LCFF_X1_Y16_N25; Fanout = 7; REG Node = 'cnt\[2\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.733 ns" { clk~clkctrl cnt[2] } "NODE_NAME" } } { "counter2.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/counter2/counter2.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.462 ns ( 50.07 % ) " "Info: Total cell delay = 1.462 ns ( 50.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.458 ns ( 49.93 % ) " "Info: Total interconnect delay = 1.458 ns ( 49.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.920 ns" { clk clk~clkctrl cnt[2] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.920 ns" { clk clk~combout clk~clkctrl cnt[2] } { 0.000ns 0.000ns 0.343ns 1.115ns } { 0.000ns 0.844ns 0.000ns 0.618ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.920 ns" { clk clk~clkctrl cnt[4] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.920 ns" { clk clk~combout clk~clkctrl cnt[4] } { 0.000ns 0.000ns 0.343ns 1.115ns } { 0.000ns 0.844ns 0.000ns 0.618ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.920 ns" { clk clk~clkctrl cnt[2] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.920 ns" { clk clk~combout clk~clkctrl cnt[2] } { 0.000ns 0.000ns 0.343ns 1.115ns } { 0.000ns 0.844ns 0.000ns 0.618ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" {  } { { "counter2.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/counter2/counter2.vhd" 30 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" {  } { { "counter2.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/counter2/counter2.vhd" 30 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.305 ns" { cnt[2] Add1~100 Add1~104 Add1~107 cnt~161 cnt[4] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "1.305 ns" { cnt[2] Add1~100 Add1~104 Add1~107 cnt~161 cnt[4] } { 0.000ns 0.309ns 0.000ns 0.000ns 0.319ns 0.000ns } { 0.000ns 0.309ns 0.035ns 0.125ns 0.053ns 0.155ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.920 ns" { clk clk~clkctrl cnt[4] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.920 ns" { clk clk~combout clk~clkctrl cnt[4] } { 0.000ns 0.000ns 0.343ns 1.115ns } { 0.000ns 0.844ns 0.000ns 0.618ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.920 ns" { clk clk~clkctrl cnt[2] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.920 ns" { clk clk~combout clk~clkctrl cnt[2] } { 0.000ns 0.000ns 0.343ns 1.115ns } { 0.000ns 0.844ns 0.000ns 0.618ns } } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { cnt[4] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { cnt[4] } {  } {  } } } { "counter2.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/counter2/counter2.vhd" 30 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "series_addr1\[0\] flag clk 2.400 ns register " "Info: tsu for register \"series_addr1\[0\]\" (data pin = \"flag\", clock pin = \"clk\") is 2.400 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.261 ns + Longest pin register " "Info: + Longest pin to register delay is 5.261 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.800 ns) 0.800 ns flag 1 PIN PIN_W7 1 " "Info: 1: + IC(0.000 ns) + CELL(0.800 ns) = 0.800 ns; Loc. = PIN_W7; Fanout = 1; PIN Node = 'flag'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { flag } "NODE_NAME" } } { "counter2.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/counter2/counter2.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.494 ns) + CELL(0.357 ns) 4.651 ns series_addr1\[0\]~50 2 COMB LCCOMB_X77_Y12_N20 5 " "Info: 2: + IC(3.494 ns) + CELL(0.357 ns) = 4.651 ns; Loc. = LCCOMB_X77_Y12_N20; Fanout = 5; COMB Node = 'series_addr1\[0\]~50'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.851 ns" { flag series_addr1[0]~50 } "NODE_NAME" } } { "counter2.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/counter2/counter2.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.213 ns) + CELL(0.397 ns) 5.261 ns series_addr1\[0\] 3 REG LCFF_X77_Y12_N1 4 " "Info: 3: + IC(0.213 ns) + CELL(0.397 ns) = 5.261 ns; Loc. = LCFF_X77_Y12_N1; Fanout = 4; REG Node = 'series_addr1\[0\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.610 ns" { series_addr1[0]~50 series_addr1[0] } "NODE_NAME" } } { "counter2.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/counter2/counter2.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.554 ns ( 29.54 % ) " "Info: Total cell delay = 1.554 ns ( 29.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.707 ns ( 70.46 % ) " "Info: Total interconnect delay = 3.707 ns ( 70.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.261 ns" { flag series_addr1[0]~50 series_addr1[0] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "5.261 ns" { flag flag~combout series_addr1[0]~50 series_addr1[0] } { 0.000ns 0.000ns 3.494ns 0.213ns } { 0.000ns 0.800ns 0.357ns 0.397ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" {  } { { "counter2.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/counter2/counter2.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.951 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.951 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.844 ns) 0.844 ns clk 1 CLK PIN_P23 1 " "Info: 1: + IC(0.000 ns) + CELL(0.844 ns) = 0.844 ns; Loc. = PIN_P23; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "counter2.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/counter2/counter2.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.187 ns clk~clkctrl 2 COMB CLKCTRL_G3 11 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.187 ns; Loc. = CLKCTRL_G3; Fanout = 11; COMB Node = 'clk~clkctrl'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "counter2.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/counter2/counter2.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.146 ns) + CELL(0.618 ns) 2.951 ns series_addr1\[0\] 3 REG LCFF_X77_Y12_N1 4 " "Info: 3: + IC(1.146 ns) + CELL(0.618 ns) = 2.951 ns; Loc. = LCFF_X77_Y12_N1; Fanout = 4; REG Node = 'series_addr1\[0\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.764 ns" { clk~clkctrl series_addr1[0] } "NODE_NAME" } } { "counter2.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/counter2/counter2.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.462 ns ( 49.54 % ) " "Info: Total cell delay = 1.462 ns ( 49.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.489 ns ( 50.46 % ) " "Info: Total interconnect delay = 1.489 ns ( 50.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.951 ns" { clk clk~clkctrl series_addr1[0] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.951 ns" { clk clk~combout clk~clkctrl series_addr1[0] } { 0.000ns 0.000ns 0.343ns 1.146ns } { 0.000ns 0.844ns 0.000ns 0.618ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.261 ns" { flag series_addr1[0]~50 series_addr1[0] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "5.261 ns" { flag flag~combout series_addr1[0]~50 series_addr1[0] } { 0.000ns 0.000ns 3.494ns 0.213ns } { 0.000ns 0.800ns 0.357ns 0.397ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.951 ns" { clk clk~clkctrl series_addr1[0] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.951 ns" { clk clk~combout clk~clkctrl series_addr1[0] } { 0.000ns 0.000ns 0.343ns 1.146ns } { 0.000ns 0.844ns 0.000ns 0.618ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk ch cnt\[4\] 6.272 ns register " "Info: tco from clock \"clk\" to destination pin \"ch\" through register \"cnt\[4\]\" is 6.272 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.920 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.920 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.844 ns) 0.844 ns clk 1 CLK PIN_P23 1 " "Info: 1: + IC(0.000 ns) + CELL(0.844 ns) = 0.844 ns; Loc. = PIN_P23; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "counter2.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/counter2/counter2.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.187 ns clk~clkctrl 2 COMB CLKCTRL_G3 11 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.187 ns; Loc. = CLKCTRL_G3; Fanout = 11; COMB Node = 'clk~clkctrl'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "counter2.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/counter2/counter2.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.115 ns) + CELL(0.618 ns) 2.920 ns cnt\[4\] 3 REG LCFF_X1_Y16_N23 3 " "Info: 3: + IC(1.115 ns) + CELL(0.618 ns) = 2.920 ns; Loc. = LCFF_X1_Y16_N23; Fanout = 3; REG Node = 'cnt\[4\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.733 ns" { clk~clkctrl cnt[4] } "NODE_NAME" } } { "counter2.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/counter2/counter2.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.462 ns ( 50.07 % ) " "Info: Total cell delay = 1.462 ns ( 50.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.458 ns ( 49.93 % ) " "Info: Total interconnect delay = 1.458 ns ( 49.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.920 ns" { clk clk~clkctrl cnt[4] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.920 ns" { clk clk~combout clk~clkctrl cnt[4] } { 0.000ns 0.000ns 0.343ns 1.115ns } { 0.000ns 0.844ns 0.000ns 0.618ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" {  } { { "counter2.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/counter2/counter2.vhd" 30 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.258 ns + Longest register pin " "Info: + Longest register to pin delay is 3.258 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt\[4\] 1 REG LCFF_X1_Y16_N23 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y16_N23; Fanout = 3; REG Node = 'cnt\[4\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { cnt[4] } "NODE_NAME" } } { "counter2.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/counter2/counter2.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.254 ns) + CELL(0.228 ns) 0.482 ns Equal1~32 2 COMB LCCOMB_X1_Y16_N30 5 " "Info: 2: + IC(0.254 ns) + CELL(0.228 ns) = 0.482 ns; Loc. = LCCOMB_X1_Y16_N30; Fanout = 5; COMB Node = 'Equal1~32'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.482 ns" { cnt[4] Equal1~32 } "NODE_NAME" } } { "counter2.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/counter2/counter2.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.244 ns) + CELL(0.053 ns) 0.779 ns LessThan0~48 3 COMB LCCOMB_X1_Y16_N28 1 " "Info: 3: + IC(0.244 ns) + CELL(0.053 ns) = 0.779 ns; Loc. = LCCOMB_X1_Y16_N28; Fanout = 1; COMB Node = 'LessThan0~48'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.297 ns" { Equal1~32 LessThan0~48 } "NODE_NAME" } } { "counter2.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/counter2/counter2.vhd" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.325 ns) + CELL(2.154 ns) 3.258 ns ch 4 PIN PIN_AA23 0 " "Info: 4: + IC(0.325 ns) + CELL(2.154 ns) = 3.258 ns; Loc. = PIN_AA23; Fanout = 0; PIN Node = 'ch'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.479 ns" { LessThan0~48 ch } "NODE_NAME" } } { "counter2.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/counter2/counter2.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.435 ns ( 74.74 % ) " "Info: Total cell delay = 2.435 ns ( 74.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.823 ns ( 25.26 % ) " "Info: Total interconnect delay = 0.823 ns ( 25.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.258 ns" { cnt[4] Equal1~32 LessThan0~48 ch } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "3.258 ns" { cnt[4] Equal1~32 LessThan0~48 ch } { 0.000ns 0.254ns 0.244ns 0.325ns } { 0.000ns 0.228ns 0.053ns 2.154ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.920 ns" { clk clk~clkctrl cnt[4] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.920 ns" { clk clk~combout clk~clkctrl cnt[4] } { 0.000ns 0.000ns 0.343ns 1.115ns } { 0.000ns 0.844ns 0.000ns 0.618ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.258 ns" { cnt[4] Equal1~32 LessThan0~48 ch } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "3.258 ns" { cnt[4] Equal1~32 LessThan0~48 ch } { 0.000ns 0.254ns 0.244ns 0.325ns } { 0.000ns 0.228ns 0.053ns 2.154ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "series_addr1\[0\] flag clk -2.161 ns register " "Info: th for register \"series_addr1\[0\]\" (data pin = \"flag\", clock pin = \"clk\") is -2.161 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.951 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.951 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.844 ns) 0.844 ns clk 1 CLK PIN_P23 1 " "Info: 1: + IC(0.000 ns) + CELL(0.844 ns) = 0.844 ns; Loc. = PIN_P23; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "counter2.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/counter2/counter2.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.187 ns clk~clkctrl 2 COMB CLKCTRL_G3 11 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.187 ns; Loc. = CLKCTRL_G3; Fanout = 11; COMB Node = 'clk~clkctrl'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "counter2.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/counter2/counter2.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.146 ns) + CELL(0.618 ns) 2.951 ns series_addr1\[0\] 3 REG LCFF_X77_Y12_N1 4 " "Info: 3: + IC(1.146 ns) + CELL(0.618 ns) = 2.951 ns; Loc. = LCFF_X77_Y12_N1; Fanout = 4; REG Node = 'series_addr1\[0\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.764 ns" { clk~clkctrl series_addr1[0] } "NODE_NAME" } } { "counter2.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/counter2/counter2.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.462 ns ( 49.54 % ) " "Info: Total cell delay = 1.462 ns ( 49.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.489 ns ( 50.46 % ) " "Info: Total interconnect delay = 1.489 ns ( 50.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.951 ns" { clk clk~clkctrl series_addr1[0] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.951 ns" { clk clk~combout clk~clkctrl series_addr1[0] } { 0.000ns 0.000ns 0.343ns 1.146ns } { 0.000ns 0.844ns 0.000ns 0.618ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.149 ns + " "Info: + Micro hold delay of destination is 0.149 ns" {  } { { "counter2.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/counter2/counter2.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.261 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.261 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.800 ns) 0.800 ns flag 1 PIN PIN_W7 1 " "Info: 1: + IC(0.000 ns) + CELL(0.800 ns) = 0.800 ns; Loc. = PIN_W7; Fanout = 1; PIN Node = 'flag'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { flag } "NODE_NAME" } } { "counter2.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/counter2/counter2.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.494 ns) + CELL(0.357 ns) 4.651 ns series_addr1\[0\]~50 2 COMB LCCOMB_X77_Y12_N20 5 " "Info: 2: + IC(3.494 ns) + CELL(0.357 ns) = 4.651 ns; Loc. = LCCOMB_X77_Y12_N20; Fanout = 5; COMB Node = 'series_addr1\[0\]~50'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.851 ns" { flag series_addr1[0]~50 } "NODE_NAME" } } { "counter2.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/counter2/counter2.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.213 ns) + CELL(0.397 ns) 5.261 ns series_addr1\[0\] 3 REG LCFF_X77_Y12_N1 4 " "Info: 3: + IC(0.213 ns) + CELL(0.397 ns) = 5.261 ns; Loc. = LCFF_X77_Y12_N1; Fanout = 4; REG Node = 'series_addr1\[0\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.610 ns" { series_addr1[0]~50 series_addr1[0] } "NODE_NAME" } } { "counter2.vhd" "" { Text "F:/liangshuo程序/1/fen_zu_interlacing/counter2/counter2.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.554 ns ( 29.54 % ) " "Info: Total cell delay = 1.554 ns ( 29.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.707 ns ( 70.46 % ) " "Info: Total interconnect delay = 3.707 ns ( 70.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.261 ns" { flag series_addr1[0]~50 series_addr1[0] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "5.261 ns" { flag flag~combout series_addr1[0]~50 series_addr1[0] } { 0.000ns 0.000ns 3.494ns 0.213ns } { 0.000ns 0.800ns 0.357ns 0.397ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.951 ns" { clk clk~clkctrl series_addr1[0] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.951 ns" { clk clk~combout clk~clkctrl series_addr1[0] } { 0.000ns 0.000ns 0.343ns 1.146ns } { 0.000ns 0.844ns 0.000ns 0.618ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.261 ns" { flag series_addr1[0]~50 series_addr1[0] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "5.261 ns" { flag flag~combout series_addr1[0]~50 series_addr1[0] } { 0.000ns 0.000ns 3.494ns 0.213ns } { 0.000ns 0.800ns 0.357ns 0.397ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}