counter2.vhd

来自「一个简单的交织实现程序」· VHDL 代码 · 共 48 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter2 is
port(clk,flag:in std_logic;
    ch:out std_logic;
   series_addr:out integer range 0 to 29);
end ;
architecture a of counter2 is
signal series_addr1:integer range 0 to 29;
signal cnt :integer range 0 to 59;
begin
process(clk,flag)
begin
if clk'event and clk='1' then
 if flag='1' then
    if (series_addr1=29 ) then
         series_addr1<=0;            
 	else  
	    series_addr1<=series_addr1+1;   
	end if; 
 else  
   series_addr1<=0; 
end if;
end if;
end process;

process(clk)
begin
if clk'event and clk='1' then
  if (cnt=59 ) then
       cnt<=0;            
 	else  
	   cnt<=cnt+1; 
  end if;
end if;
end process;

process(cnt)
begin
 if (cnt<=29) then
      ch<='1';
 else ch<='0';
 end if;
end process;

series_addr<=series_addr1;
end a;