counter2.tan.rpt

一个简单的交织实现程序

; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cnt[5]          ; cnt[2]          ; clk        ; clk      ; None                        ; None                      ; 0.825 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cnt[5]          ; cnt[3]          ; clk        ; clk      ; None                        ; None                      ; 0.825 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cnt[5]          ; cnt[4]          ; clk        ; clk      ; None                        ; None                      ; 0.720 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cnt[0]          ; cnt[1]          ; clk        ; clk      ; None                        ; None                      ; 0.680 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cnt[0]          ; cnt[0]          ; clk        ; clk      ; None                        ; None                      ; 0.609 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cnt[1]          ; cnt[1]          ; clk        ; clk      ; None                        ; None                      ; 0.609 ns                ;
+-------+------------------------------------------------+-----------------+-----------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-----------------------------------------------------------------------+
; tsu                                                                   ;
+-------+--------------+------------+------+-----------------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To              ; To Clock ;
+-------+--------------+------------+------+-----------------+----------+
; N/A   ; None         ; 2.400 ns   ; flag ; series_addr1[0] ; clk      ;
; N/A   ; None         ; 2.400 ns   ; flag ; series_addr1[4] ; clk      ;
; N/A   ; None         ; 2.400 ns   ; flag ; series_addr1[3] ; clk      ;
; N/A   ; None         ; 2.400 ns   ; flag ; series_addr1[1] ; clk      ;
; N/A   ; None         ; 2.400 ns   ; flag ; series_addr1[2] ; clk      ;
+-------+--------------+------------+------+-----------------+----------+


+-----------------------------------------------------------------------------------+
; tco                                                                               ;
+-------+--------------+------------+-----------------+----------------+------------+
; Slack ; Required tco ; Actual tco ; From            ; To             ; From Clock ;
+-------+--------------+------------+-----------------+----------------+------------+
; N/A   ; None         ; 6.272 ns   ; cnt[4]          ; ch             ; clk        ;
; N/A   ; None         ; 6.226 ns   ; cnt[1]          ; ch             ; clk        ;
; N/A   ; None         ; 6.106 ns   ; cnt[2]          ; ch             ; clk        ;
; N/A   ; None         ; 6.075 ns   ; cnt[3]          ; ch             ; clk        ;
; N/A   ; None         ; 6.007 ns   ; cnt[5]          ; ch             ; clk        ;
; N/A   ; None         ; 5.922 ns   ; series_addr1[1] ; series_addr[1] ; clk        ;
; N/A   ; None         ; 5.817 ns   ; series_addr1[4] ; series_addr[4] ; clk        ;
; N/A   ; None         ; 5.524 ns   ; series_addr1[3] ; series_addr[3] ; clk        ;
; N/A   ; None         ; 5.523 ns   ; series_addr1[2] ; series_addr[2] ; clk        ;
; N/A   ; None         ; 5.501 ns   ; series_addr1[0] ; series_addr[0] ; clk        ;
+-------+--------------+------------+-----------------+----------------+------------+


+-----------------------------------------------------------------------------+
; th                                                                          ;
+---------------+-------------+-----------+------+-----------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To              ; To Clock ;
+---------------+-------------+-----------+------+-----------------+----------+
; N/A           ; None        ; -2.161 ns ; flag ; series_addr1[0] ; clk      ;
; N/A           ; None        ; -2.161 ns ; flag ; series_addr1[4] ; clk      ;
; N/A           ; None        ; -2.161 ns ; flag ; series_addr1[3] ; clk      ;
; N/A           ; None        ; -2.161 ns ; flag ; series_addr1[1] ; clk      ;
; N/A           ; None        ; -2.161 ns ; flag ; series_addr1[2] ; clk      ;
+---------------+-------------+-----------+------+-----------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Tue Apr 08 23:26:08 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off counter2 -c counter2 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 500.0 MHz between source register "cnt[2]" and destination register "cnt[4]"
    Info: fmax restricted to clock pin edge rate 2.0 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.305 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y16_N25; Fanout = 7; REG Node = 'cnt[2]'
            Info: 2: + IC(0.309 ns) + CELL(0.309 ns) = 0.618 ns; Loc. = LCCOMB_X1_Y16_N4; Fanout = 2; COMB Node = 'Add1~100'
            Info: 3: + IC(0.000 ns) + CELL(0.035 ns) = 0.653 ns; Loc. = LCCOMB_X1_Y16_N6; Fanout = 2; COMB Node = 'Add1~104'
            Info: 4: + IC(0.000 ns) + CELL(0.125 ns) = 0.778 ns; Loc. = LCCOMB_X1_Y16_N8; Fanout = 1; COMB Node = 'Add1~107'
            Info: 5: + IC(0.319 ns) + CELL(0.053 ns) = 1.150 ns; Loc. = LCCOMB_X1_Y16_N22; Fanout = 1; COMB Node = 'cnt~161'
            Info: 6: + IC(0.000 ns) + CELL(0.155 ns) = 1.305 ns; Loc. = LCFF_X1_Y16_N23; Fanout = 3; REG Node = 'cnt[4]'
            Info: Total cell delay = 0.677 ns ( 51.88 % )
            Info: Total interconnect delay = 0.628 ns ( 48.12 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.920 ns
                Info: 1: + IC(0.000 ns) + CELL(0.844 ns) = 0.844 ns; Loc. = PIN_P23; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.187 ns; Loc. = CLKCTRL_G3; Fanout = 11; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(1.115 ns) + CELL(0.618 ns) = 2.920 ns; Loc. = LCFF_X1_Y16_N23; Fanout = 3; REG Node = 'cnt[4]'
                Info: Total cell delay = 1.462 ns ( 50.07 % )
                Info: Total interconnect delay = 1.458 ns ( 49.93 % )
            Info: - Longest clock path from clock "clk" to source register is 2.920 ns
                Info: 1: + IC(0.000 ns) + CELL(0.844 ns) = 0.844 ns; Loc. = PIN_P23; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.187 ns; Loc. = CLKCTRL_G3; Fanout = 11; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(1.115 ns) + CELL(0.618 ns) = 2.920 ns; Loc. = LCFF_X1_Y16_N25; Fanout = 7; REG Node = 'cnt[2]'
                Info: Total cell delay = 1.462 ns ( 50.07 % )
                Info: Total interconnect delay = 1.458 ns ( 49.93 % )
        Info: + Micro clock to output delay of source is 0.094 ns
        Info: + Micro setup delay of destination is 0.090 ns
Info: tsu for register "series_addr1[0]" (data pin = "flag", clock pin = "clk") is 2.400 ns
    Info: + Longest pin to register delay is 5.261 ns
        Info: 1: + IC(0.000 ns) + CELL(0.800 ns) = 0.800 ns; Loc. = PIN_W7; Fanout = 1; PIN Node = 'flag'
        Info: 2: + IC(3.494 ns) + CELL(0.357 ns) = 4.651 ns; Loc. = LCCOMB_X77_Y12_N20; Fanout = 5; COMB Node = 'series_addr1[0]~50'
        Info: 3: + IC(0.213 ns) + CELL(0.397 ns) = 5.261 ns; Loc. = LCFF_X77_Y12_N1; Fanout = 4; REG Node = 'series_addr1[0]'
        Info: Total cell delay = 1.554 ns ( 29.54 % )
        Info: Total interconnect delay = 3.707 ns ( 70.46 % )
    Info: + Micro setup delay of destination is 0.090 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.951 ns
        Info: 1: + IC(0.000 ns) + CELL(0.844 ns) = 0.844 ns; Loc. = PIN_P23; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.187 ns; Loc. = CLKCTRL_G3; Fanout = 11; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(1.146 ns) + CELL(0.618 ns) = 2.951 ns; Loc. = LCFF_X77_Y12_N1; Fanout = 4; REG Node = 'series_addr1[0]'
        Info: Total cell delay = 1.462 ns ( 49.54 % )
        Info: Total interconnect delay = 1.489 ns ( 50.46 % )
Info: tco from clock "clk" to destination pin "ch" through register "cnt[4]" is 6.272 ns
    Info: + Longest clock path from clock "clk" to source register is 2.920 ns
        Info: 1: + IC(0.000 ns) + CELL(0.844 ns) = 0.844 ns; Loc. = PIN_P23; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.187 ns; Loc. = CLKCTRL_G3; Fanout = 11; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(1.115 ns) + CELL(0.618 ns) = 2.920 ns; Loc. = LCFF_X1_Y16_N23; Fanout = 3; REG Node = 'cnt[4]'
        Info: Total cell delay = 1.462 ns ( 50.07 % )
        Info: Total interconnect delay = 1.458 ns ( 49.93 % )
    Info: + Micro clock to output delay of source is 0.094 ns
    Info: + Longest register to pin delay is 3.258 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y16_N23; Fanout = 3; REG Node = 'cnt[4]'
        Info: 2: + IC(0.254 ns) + CELL(0.228 ns) = 0.482 ns; Loc. = LCCOMB_X1_Y16_N30; Fanout = 5; COMB Node = 'Equal1~32'
        Info: 3: + IC(0.244 ns) + CELL(0.053 ns) = 0.779 ns; Loc. = LCCOMB_X1_Y16_N28; Fanout = 1; COMB Node = 'LessThan0~48'
        Info: 4: + IC(0.325 ns) + CELL(2.154 ns) = 3.258 ns; Loc. = PIN_AA23; Fanout = 0; PIN Node = 'ch'
        Info: Total cell delay = 2.435 ns ( 74.74 % )
        Info: Total interconnect delay = 0.823 ns ( 25.26 % )
Info: th for register "series_addr1[0]" (data pin = "flag", clock pin = "clk") is -2.161 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.951 ns
        Info: 1: + IC(0.000 ns) + CELL(0.844 ns) = 0.844 ns; Loc. = PIN_P23; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.187 ns; Loc. = CLKCTRL_G3; Fanout = 11; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(1.146 ns) + CELL(0.618 ns) = 2.951 ns; Loc. = LCFF_X77_Y12_N1; Fanout = 4; REG Node = 'series_addr1[0]'
        Info: Total cell delay = 1.462 ns ( 49.54 % )
        Info: Total interconnect delay = 1.489 ns ( 50.46 % )
    Info: + Micro hold delay of destination is 0.149 ns
    Info: - Shortest pin to register delay is 5.261 ns
        Info: 1: + IC(0.000 ns) + CELL(0.800 ns) = 0.800 ns; Loc. = PIN_W7; Fanout = 1; PIN Node = 'flag'
        Info: 2: + IC(3.494 ns) + CELL(0.357 ns) = 4.651 ns; Loc. = LCCOMB_X77_Y12_N20; Fanout = 5; COMB Node = 'series_addr1[0]~50'
        Info: 3: + IC(0.213 ns) + CELL(0.397 ns) = 5.261 ns; Loc. = LCFF_X77_Y12_N1; Fanout = 4; REG Node = 'series_addr1[0]'
        Info: Total cell delay = 1.554 ns ( 29.54 % )
        Info: Total interconnect delay = 3.707 ns ( 70.46 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Tue Apr 08 23:26:08 2008
    Info: Elapsed time: 00:00:01