📄 counter2.tan.rpt
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Timing Analyzer report for counter2
Tue Apr 08 23:26:08 2008
Version 6.0 Build 178 04/27/2006 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'clk'
6. tsu
7. tco
8. th
9. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+------------------------------------------------+--------+-----------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+--------+-----------------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 2.400 ns ; flag ; series_addr1[2] ; -- ; clk ; 0 ;
; Worst-case tco ; N/A ; None ; 6.272 ns ; cnt[4] ; ch ; clk ; -- ; 0 ;
; Worst-case th ; N/A ; None ; -2.161 ns ; flag ; series_addr1[2] ; -- ; clk ; 0 ;
; Clock Setup: 'clk' ; N/A ; None ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cnt[2] ; cnt[4] ; clk ; clk ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+------------------------------------------------+--------+-----------------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP2S60F672C3 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk' ;
+-------+------------------------------------------------+-----------------+-----------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+-----------------+-----------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cnt[2] ; cnt[4] ; clk ; clk ; None ; None ; 1.305 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cnt[2] ; cnt[3] ; clk ; clk ; None ; None ; 1.277 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cnt[2] ; cnt[5] ; clk ; clk ; None ; None ; 1.276 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; series_addr1[4] ; series_addr1[0] ; clk ; clk ; None ; None ; 1.266 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; series_addr1[4] ; series_addr1[4] ; clk ; clk ; None ; None ; 1.266 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; series_addr1[4] ; series_addr1[3] ; clk ; clk ; None ; None ; 1.266 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; series_addr1[4] ; series_addr1[1] ; clk ; clk ; None ; None ; 1.266 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; series_addr1[4] ; series_addr1[2] ; clk ; clk ; None ; None ; 1.266 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cnt[0] ; cnt[4] ; clk ; clk ; None ; None ; 1.215 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cnt[4] ; cnt[4] ; clk ; clk ; None ; None ; 1.201 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cnt[4] ; cnt[5] ; clk ; clk ; None ; None ; 1.200 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cnt[3] ; cnt[4] ; clk ; clk ; None ; None ; 1.196 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cnt[0] ; cnt[3] ; clk ; clk ; None ; None ; 1.187 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cnt[0] ; cnt[5] ; clk ; clk ; None ; None ; 1.186 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cnt[1] ; cnt[4] ; clk ; clk ; None ; None ; 1.180 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cnt[4] ; cnt[3] ; clk ; clk ; None ; None ; 1.178 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cnt[3] ; cnt[5] ; clk ; clk ; None ; None ; 1.167 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cnt[1] ; cnt[3] ; clk ; clk ; None ; None ; 1.152 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cnt[1] ; cnt[5] ; clk ; clk ; None ; None ; 1.151 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cnt[4] ; cnt[2] ; clk ; clk ; None ; None ; 1.145 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cnt[2] ; cnt[2] ; clk ; clk ; None ; None ; 1.143 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cnt[3] ; cnt[3] ; clk ; clk ; None ; None ; 1.140 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; series_addr1[3] ; series_addr1[0] ; clk ; clk ; None ; None ; 1.139 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; series_addr1[3] ; series_addr1[4] ; clk ; clk ; None ; None ; 1.139 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; series_addr1[3] ; series_addr1[3] ; clk ; clk ; None ; None ; 1.139 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; series_addr1[3] ; series_addr1[1] ; clk ; clk ; None ; None ; 1.139 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; series_addr1[3] ; series_addr1[2] ; clk ; clk ; None ; None ; 1.139 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; series_addr1[0] ; series_addr1[0] ; clk ; clk ; None ; None ; 1.132 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; series_addr1[0] ; series_addr1[4] ; clk ; clk ; None ; None ; 1.132 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; series_addr1[0] ; series_addr1[3] ; clk ; clk ; None ; None ; 1.132 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; series_addr1[0] ; series_addr1[1] ; clk ; clk ; None ; None ; 1.132 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; series_addr1[0] ; series_addr1[2] ; clk ; clk ; None ; None ; 1.132 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cnt[1] ; cnt[2] ; clk ; clk ; None ; None ; 1.099 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cnt[5] ; cnt[5] ; clk ; clk ; None ; None ; 1.086 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cnt[0] ; cnt[2] ; clk ; clk ; None ; None ; 1.081 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; series_addr1[1] ; series_addr1[0] ; clk ; clk ; None ; None ; 0.983 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; series_addr1[1] ; series_addr1[4] ; clk ; clk ; None ; None ; 0.983 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; series_addr1[1] ; series_addr1[3] ; clk ; clk ; None ; None ; 0.983 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; series_addr1[1] ; series_addr1[1] ; clk ; clk ; None ; None ; 0.983 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; series_addr1[1] ; series_addr1[2] ; clk ; clk ; None ; None ; 0.983 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; cnt[3] ; cnt[2] ; clk ; clk ; None ; None ; 0.948 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; series_addr1[2] ; series_addr1[0] ; clk ; clk ; None ; None ; 0.875 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; series_addr1[2] ; series_addr1[4] ; clk ; clk ; None ; None ; 0.875 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; series_addr1[2] ; series_addr1[3] ; clk ; clk ; None ; None ; 0.875 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; series_addr1[2] ; series_addr1[1] ; clk ; clk ; None ; None ; 0.875 ns ;
; N/A ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; series_addr1[2] ; series_addr1[2] ; clk ; clk ; None ; None ; 0.875 ns ;
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