interlace.fit.talkback.xml

一个简单的交织实现程序

	<row>
		<i_o_bank>2</i_o_bank>
		<usage>9 / 30 ( 30 % )</usage>
		<vccio_voltage>3.3V</vccio_voltage>
	</row>
	<row>
		<i_o_bank>3</i_o_bank>
		<usage>14 / 51 ( 27 % )</usage>
		<vccio_voltage>3.3V</vccio_voltage>
	</row>
	<row>
		<i_o_bank>4</i_o_bank>
		<usage>1 / 52 ( 2 % )</usage>
		<vccio_voltage>3.3V</vccio_voltage>
	</row>
	<row>
		<i_o_bank>5</i_o_bank>
		<usage>1 / 29 ( 3 % )</usage>
		<vccio_voltage>3.3V</vccio_voltage>
	</row>
	<row>
		<i_o_bank>6</i_o_bank>
		<usage>0 / 29 ( 0 % )</usage>
		<vccio_voltage>3.3V</vccio_voltage>
	</row>
	<row>
		<i_o_bank>7</i_o_bank>
		<usage>0 / 52 ( 0 % )</usage>
		<vccio_voltage>3.3V</vccio_voltage>
	</row>
	<row>
		<i_o_bank>8</i_o_bank>
		<usage>2 / 51 ( 4 % )</usage>
		<vccio_voltage>3.3V</vccio_voltage>
	</row>
	<row>
		<i_o_bank>9</i_o_bank>
		<usage>0 / 6 ( 0 % )</usage>
		<vccio_voltage>3.3V</vccio_voltage>
	</row>
	<row>
		<i_o_bank>11</i_o_bank>
		<usage>0 / 6 ( 0 % )</usage>
		<vccio_voltage>3.3V</vccio_voltage>
	</row>
</i_o_bank_usage>
<advanced_data___general>
	<row>
		<name>Status Code</name>
		<value>0</value>
	</row>
	<row>
		<name>Desired User Slack</name>
		<value>0</value>
	</row>
	<row>
		<name>Fit Attempts</name>
		<value>1</value>
	</row>
</advanced_data___general>
<advanced_data___placement_preparation>
	<row>
		<name>Auto Fit Point 1 - Fit Attempt 1</name>
		<value>ff</value>
	</row>
	<row>
		<name>Mid Wire Use - Fit Attempt 1</name>
		<value>0</value>
	</row>
	<row>
		<name>Mid Slack - Fit Attempt 1</name>
		<value>995494</value>
	</row>
	<row>
		<name>Internal Atom Count - Fit Attempt 1</name>
		<value>35</value>
	</row>
	<row>
		<name>LE/ALM Count - Fit Attempt 1</name>
		<value>35</value>
	</row>
	<row>
		<name>LAB Count - Fit Attempt 1</name>
		<value>6</value>
	</row>
	<row>
		<name>Outputs per Lab - Fit Attempt 1</name>
		<value>5.833</value>
	</row>
	<row>
		<name>Inputs per LAB - Fit Attempt 1</name>
		<value>5.833</value>
	</row>
	<row>
		<name>Global Inputs per LAB - Fit Attempt 1</name>
		<value>0.667</value>
	</row>
	<row>
		<name>LAB Constraint &apos;non-global clock / CE pair + async load&apos; - Fit Attempt 1</name>
		<value>0:6</value>
	</row>
	<row>
		<name>LAB Constraint &apos;ce + sync load&apos; - Fit Attempt 1</name>
		<value>0:6</value>
	</row>
	<row>
		<name>LAB Constraint &apos;non-global controls&apos; - Fit Attempt 1</name>
		<value>0:6</value>
	</row>
	<row>
		<name>LAB Constraint &apos;un-route combination&apos; - Fit Attempt 1</name>
		<value>0:6</value>
	</row>
	<row>
		<name>LAB Constraint &apos;non-global with asyn_clear&apos; - Fit Attempt 1</name>
		<value>0:6</value>
	</row>
	<row>
		<name>LAB Constraint &apos;un-route with async_clear&apos; - Fit Attempt 1</name>
		<value>0:6</value>
	</row>
	<row>
		<name>LAB Constraint &apos;non-global async clear + sync clear&apos; - Fit Attempt 1</name>
		<value>0:6</value>
	</row>
	<row>
		<name>LAB Constraint &apos;global non-clock/non-asynch_clear&apos; - Fit Attempt 1</name>
		<value>0:6</value>
	</row>
	<row>
		<name>LAB Constraint &apos;ygr_cl_ngclk_gclkce_sload_aload_constraint&apos; - Fit Attempt 1</name>
		<value>0:6</value>
	</row>
	<row>
		<name>LAB Constraint &apos;global control signals&apos; - Fit Attempt 1</name>
		<value>0:2;1:4</value>
	</row>
	<row>
		<name>LAB Constraint &apos;clock / ce pair constraint&apos; - Fit Attempt 1</name>
		<value>0:2;1:4</value>
	</row>
	<row>
		<name>LAB Constraint &apos;aload_aclr pair with aload used&apos; - Fit Attempt 1</name>
		<value>0:6</value>
	</row>
	<row>
		<name>LAB Constraint &apos;aload_aclr pair&apos; - Fit Attempt 1</name>
		<value>0:2;1:4</value>
	</row>
	<row>
		<name>LAB Constraint &apos;sload_sclear pair&apos; - Fit Attempt 1</name>
		<value>0:2;1:4</value>
	</row>
	<row>
		<name>LAB Constraint &apos;invert_a constraint&apos; - Fit Attempt 1</name>
		<value>0:2;1:4</value>
	</row>
	<row>
		<name>LAB Constraint &apos;has placement constraint&apos; - Fit Attempt 1</name>
		<value>0:6</value>
	</row>
	<row>
		<name>LEs in Chains - Fit Attempt 1</name>
		<value>16</value>
	</row>
	<row>
		<name>LEs in Long Chains - Fit Attempt 1</name>
		<value>0</value>
	</row>
	<row>
		<name>LABs with Chains - Fit Attempt 1</name>
		<value>2</value>
	</row>
	<row>
		<name>LABs with Multiple Chains - Fit Attempt 1</name>
		<value>0</value>
	</row>
	<row>
		<name>Time - Fit Attempt 1</name>
		<value>0</value>
	</row>
</advanced_data___placement_preparation>
<advanced_data___placement>
	<row>
		<name>Auto Fit Point 2 - Fit Attempt 1</name>
		<value>ff</value>
	</row>
	<row>
		<name>Early Wire Use - Fit Attempt 1</name>
		<value>0</value>
	</row>
	<row>
		<name>Early Slack - Fit Attempt 1</name>
		<value>994959</value>
	</row>
	<row>
		<name>Auto Fit Point 3 - Fit Attempt 1</name>
		<value>ff</value>
	</row>
	<row>
		<name>Mid Wire Use - Fit Attempt 1</name>
		<value>0</value>
	</row>
	<row>
		<name>Mid Slack - Fit Attempt 1</name>
		<value>995515</value>
	</row>
	<row>
		<name>Auto Fit Point 4 - Fit Attempt 1</name>
		<value>ff</value>
	</row>
	<row>
		<name>Late Wire Use - Fit Attempt 1</name>
		<value>0</value>
	</row>
	<row>
		<name>Late Slack - Fit Attempt 1</name>
		<value>995515</value>
	</row>
	<row>
		<name>Auto Fit Point 5 - Fit Attempt 1</name>
		<value>ff</value>
	</row>
	<row>
		<name>Time - Fit Attempt 1</name>
		<value>0</value>
	</row>
	<row>
		<name>Time in tsm_dat.dll - Fit Attempt 1</name>
		<value>0.062</value>
	</row>
	<row>
		<name>Time in tsm_tan.dll - Fit Attempt 1</name>
		<value>0.047</value>
	</row>
</advanced_data___placement>
<advanced_data___routing>
	<row>
		<name>Early Slack - Fit Attempt 1</name>
		<value>994966</value>
	</row>
	<row>
		<name>Early Wire Use - Fit Attempt 1</name>
		<value>0</value>
	</row>
	<row>
		<name>Peak Regional Wire - Fit Attempt 1</name>
		<value>1</value>
	</row>
	<row>
		<name>Mid Slack - Fit Attempt 1</name>
		<value>994727</value>
	</row>
	<row>
		<name>Late Slack - Fit Attempt 1</name>
		<value>994727</value>
	</row>
	<row>
		<name>Late Slack - Fit Attempt 1</name>
		<value>994727</value>
	</row>
	<row>
		<name>Late Wire Use - Fit Attempt 1</name>
		<value>0</value>
	</row>
	<row>
		<name>Time - Fit Attempt 1</name>
		<value>1</value>
	</row>
	<row>
		<name>Time in tsm_tan.dll - Fit Attempt 1</name>
		<value>0.109</value>
	</row>
</advanced_data___routing>
<compilation_summary>
	<flow_status>Successful - Sat Jul 22 12:18:56 2006</flow_status>
	<quartus_ii_version>5.1 Build 176 10/26/2005 SJ Web Edition</quartus_ii_version>
	<revision_name>interlace</revision_name>
	<top_level_entity_name>interlace</top_level_entity_name>
	<family>Stratix</family>
	<met_timing_requirements>N/A</met_timing_requirements>
	<total_logic_elements>34 / 10,570 ( &lt; 1 % )</total_logic_elements>
	<total_pins>30 / 336 ( 9 % )</total_pins>
	<total_virtual_pins>0</total_virtual_pins>
	<total_memory_bits>3,072 / 920,448 ( &lt; 1 % )</total_memory_bits>
	<dsp_block_9_bit_elements>0 / 48 ( 0 % )</dsp_block_9_bit_elements>
	<total_plls>0 / 6 ( 0 % )</total_plls>
	<total_dlls>0 / 2 ( 0 % )</total_dlls>
	<device>EP1S10F484C5</device>
	<timing_models>Final</timing_models>
</compilation_summary>
<compile_id>46A308F</compile_id>
<files>
	<top>D:/altera/interlacing/interlace.bdf</top>
	<extensions>
		<ext filename="none">1</ext>
		<ext ext_name="bdf">1</ext>
		<ext ext_name="vwf">2</ext>
		<ext ext_name="vhd">4</ext>
		<ext ext_name="tdf">3</ext>
		<ext ext_name="inc">10</ext>
		<ext ext_name="lst">1</ext>
		<ext ext_name="v">2</ext>
		<ext ext_name="mif">1</ext>
	</extensions>
	<sub_files>
		<sub_file>D:/altera/interlacing/interlace.bdf</sub_file>
		<sub_file>D:/altera/interlacing/interlace.vwf</sub_file>
		<sub_file>D:/altera/interlacing/Waveform1.vwf</sub_file>
		<sub_file>D:/altera/interlacing/RAM_MN_dual.vhd</sub_file>
		<sub_file>d:/altera/quartus51/libraries/megafunctions/altsyncram.tdf</sub_file>
		<sub_file>d:/altera/quartus51/libraries/megafunctions/stratix_ram_block.inc</sub_file>
		<sub_file>d:/altera/quartus51/libraries/megafunctions/lpm_mux.inc</sub_file>
		<sub_file>d:/altera/quartus51/libraries/megafunctions/lpm_decode.inc</sub_file>
		<sub_file>d:/altera/quartus51/libraries/megafunctions/aglobal51.inc</sub_file>
		<sub_file>d:/altera/quartus51/libraries/megafunctions/altsyncram.inc</sub_file>
		<sub_file>d:/altera/quartus51/libraries/megafunctions/a_rdenreg.inc</sub_file>
		<sub_file>d:/altera/quartus51/libraries/megafunctions/altrom.inc</sub_file>
		<sub_file>d:/altera/quartus51/libraries/megafunctions/altram.inc</sub_file>
		<sub_file>d:/altera/quartus51/libraries/megafunctions/altdpram.inc</sub_file>
		<sub_file>d:/altera/quartus51/libraries/megafunctions/altqpram.inc</sub_file>
		<sub_file>d:/altera/quartus51/libraries/megafunctions/cbx.lst</sub_file>
		<sub_file>D:/altera/interlacing/db/altsyncram_5d81.tdf</sub_file>
		<sub_file>none</sub_file>
		<sub_file>D:/altera/interlacing/counter.v</sub_file>
		<sub_file>D:/altera/interlacing/rom_mn_interlace.vhd</sub_file>
		<sub_file>D:/altera/interlacing/rom_mn_seq.vhd</sub_file>
		<sub_file>D:/altera/interlacing/RAM_MN_dual2.vhd</sub_file>
		<sub_file>D:/altera/interlacing/cobination.v</sub_file>
		<sub_file>D:/altera/interlacing/db/altsyncram_ijl.tdf</sub_file>
		<sub_file>D:/altera/interlacing/db/interlace0.rtl.mif</sub_file>
	</sub_files>
</files>
<architecture>
	<family>Stratix</family>
	<auto_device>ON</auto_device>
	<device>EP1S10F484C5</device>
</architecture>
<pkg_io>
	<pin_std count="31">LVTTL</pin_std>
</pkg_io>
<research>
	<le_sclr>0</le_sclr>
	<le_aclr>17</le_aclr>
	<le_aload>0</le_aload>
	<le_sload>7</le_sload>
	<le_inverta>0</le_inverta>
	<le_carry_in>6</le_carry_in>
	<le_ce>0</le_ce>
	<le_clk>17</le_clk>
	<le_ce_sload>0</le_ce_sload>
	<pin_sclr>0</pin_sclr>
	<pin_aclr>0</pin_aclr>
	<pin_ce_in>0</pin_ce_in>
	<pin_ce_out>0</pin_ce_out>
</research>
</talkback>