📄 smallcore.fit.rpt
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Fitter report for SmallCore
Wed Aug 16 18:03:21 2006
Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version
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; Table of Contents ;
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1. Legal Notice
2. Fitter Summary
3. Fitter Settings
4. Fitter Device Options
5. Fitter Netlist Optimizations
6. Fitter Equations
7. Pin-Out File
8. Fitter Resource Usage Summary
9. Input Pins
10. Output Pins
11. Bidir Pins
12. I/O Bank Usage
13. All Package Pins
14. PLL Summary
15. PLL Usage
16. Output Pin Default Load For Reported TCO
17. Fitter Resource Utilization by Entity
18. Delay Chain Summary
19. Pad To Core Delay Chain Fanout
20. Control Signals
21. Global & Other Fast Signals
22. Non-Global High Fan-Out Signals
23. Fitter RAM Summary
24. Interconnect Usage Summary
25. LAB Logic Elements
26. LAB-wide Signals
27. LAB Signals Sourced
28. LAB Signals Sourced Out
29. LAB Distinct Inputs
30. Fitter Messages
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; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------+
; Fitter Summary ;
+-----------------------+-----------------------------------------------+
; Fitter Status ; Successful - Wed Aug 16 18:03:21 2006 ;
; Quartus II Version ; 5.0 Build 168 06/22/2005 SP 1 SJ Full Version ;
; Revision Name ; SmallCore ;
; Top-level Entity Name ; SmallCore ;
; Family ; Cyclone ;
; Device ; EP1C6Q240C8 ;
; Timing Models ; Final ;
; Total logic elements ; 1,920 / 5,980 ( 32 % ) ;
; Total pins ; 50 / 185 ( 27 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 10,240 / 92,160 ( 11 % ) ;
; Total PLLs ; 1 / 2 ( 50 % ) ;
+-----------------------+-----------------------------------------------+
+----------------------------------------------------------------------------------------------------------------------+
; Fitter Settings ;
+----------------------------------------------------+--------------------------------+--------------------------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------+--------------------------------+--------------------------------+
; Device ; EP1C6Q240C8 ; ;
; Optimize Fast-Corner Timing ; On ; Off ;
; Fitter Effort ; Fast Fit ; Auto Fit ;
; Use smart compilation ; Off ; Off ;
; Placement Effort Multiplier ; 1.0 ; 1.0 ;
; Router Effort Multiplier ; 1.0 ; 1.0 ;
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