smallcore.tan.rpt

周立功:SOPC嵌入式系统实验教程（一）部分章节及实验代码

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
+--------------------------------------------------------+-----------+----------------------------------+----------------------------------+----------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------+-----------------------------------------+--------------+
; Type                                                   ; Slack     ; Required Time                    ; Actual Time                      ; From                                                                                                           ; To                                                                                                                                                                                  ; From Clock                              ; To Clock                                ; Failed Paths ;
+--------------------------------------------------------+-----------+----------------------------------+----------------------------------+----------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------+-----------------------------------------+--------------+
; Worst-case tsu                                         ; N/A       ; None                             ; 4.558 ns                         ; altera_internal_jtag~SHIFTUSER                                                                                 ; nios2e_1C6:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[16] ;                                         ; altera_internal_jtag~TCKUTAP            ; 0            ;
; Worst-case tco                                         ; N/A       ; None                             ; 7.420 ns                         ; nios2e_1C6:inst|led_pio:the_led_pio|data_out[4]                                                                ; LED_PIO[4]                                                                                                                                                                          ; SYS_CLK2                                ;                                         ; 0            ;
; Worst-case tpd                                         ; N/A       ; None                             ; 2.124 ns                         ; altera_internal_jtag~TDO                                                                                       ; altera_reserved_tdo                                                                                                                                                                 ;                                         ;                                         ; 0            ;
; Worst-case th                                          ; N/A       ; None                             ; 3.982 ns                         ; altera_internal_jtag~TDIUTAP                                                                                   ; sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[9]                                                                                                                          ;                                         ; altera_internal_jtag~TCKUTAP            ; 0            ;
; Clock Setup: 'pll:inst1|altpll:altpll_component|_clk0' ; 7.939 ns  ; 48.00 MHz ( period = 20.833 ns ) ; 77.56 MHz ( period = 12.894 ns ) ; nios2e_1C6:inst|cpu:the_cpu|F_pc[16]                                                                           ; nios2e_1C6:inst|cpu:the_cpu|av_ld_byte0_data[2]                                                                                                                                     ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0            ;
; Clock Setup: 'SYS_CLK2'                                ; 16.325 ns ; 48.00 MHz ( period = 20.833 ns ) ; 221.83 MHz ( period = 4.508 ns ) ; delay_reset_block:inst6|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_df8:auto_generated|safe_q[1] ; delay_reset_block:inst6|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_df8:auto_generated|safe_q[0]                                                                      ; SYS_CLK2                                ; SYS_CLK2                                ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP'            ; N/A       ; None                             ; 87.40 MHz ( period = 11.442 ns ) ; sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[1]                                        ; nios2e_1C6:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|ir[1]  ; altera_internal_jtag~TCKUTAP            ; altera_internal_jtag~TCKUTAP            ; 0            ;
; Clock Hold: 'pll:inst1|altpll:altpll_component|_clk0'  ; 0.822 ns  ; 48.00 MHz ( period = 20.833 ns ) ; N/A                              ; nios2e_1C6:inst|cpu:the_cpu|av_ld_aligning_data                                                                ; nios2e_1C6:inst|cpu:the_cpu|av_ld_aligning_data                                                                                                                                     ; pll:inst1|altpll:altpll_component|_clk0 ; pll:inst1|altpll:altpll_component|_clk0 ; 0            ;
; Clock Hold: 'SYS_CLK2'                                 ; 1.312 ns  ; 48.00 MHz ( period = 20.833 ns ) ; N/A                              ; delay_reset_block:inst6|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_df8:auto_generated|safe_q[0] ; delay_reset_block:inst6|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_df8:auto_generated|safe_q[0]                                                                      ; SYS_CLK2                                ; SYS_CLK2                                ; 0            ;
; Total number of failed paths                           ;           ;                                  ;                                  ;                                                                                                                ;                                                                                                                                                                                     ;                                         ;                                         ; 0            ;
+--------------------------------------------------------+-----------+----------------------------------+----------------------------------+----------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------+-----------------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C6Q240C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;