ixp425.h

ixp425 bsp for vxworks

/* ixp425.h - Ixp425 header file */

/* Copyright 2002 Wind River Systems, Inc. */

/*
modification history
--------------------
01b,24jul03,m_h  PSM now named NPE
01a,05jun02,jb  initial version...
01b,02jul03,m_h  little endian (pbit)
*/

#ifndef INCixpIxp425h
#define INCixpIxp425h

#ifndef _ASMLANGUAGE
#else
#endif

#ifdef __cplusplus
extern "C" {
#endif

/*
 * IXP425_SDRAM_CONFIG_BASEDESCRIPTION
 * This file contains Ixp425 register definitions
 */

/* Defintion for Bit macro */
#ifndef BIT    
#define BIT(bitNumber)		(1 << (bitNumber))
#endif /* BIT */


/* Chip Level Definitions */


/* Configuration Space Registers */
#define IXP425_SDRAM_CONFIG_BASE	(0xCC000000)
#define IXP425_EXP_CONFIG_BASE		(0xC4000000)
#define IXP425_PCI_CONFIG_BASE		(0xC0000000)

/* Expansion Register Block Size */
#define IXP425_EXP_CONFIG_SIZE         (0x1000)

#define IXP425_MAX_PCI_DEVS 4

/* Peripheral Space Registers */
#define IXP425_PERIPHERAL_BASE  (0xC8000000)
#define IXP425_PERIPHERAL_SIZE  (0x10000)

#define IXP425_QMGR_BASE        (0x60000000)
#define IXP425_QMGR_SIZE        (0x4000)

#define IXP425_UART1_BASE	(IXP425_PERIPHERAL_BASE + 0x00000000)
 
#define IXP425_UART2_BASE	(IXP425_PERIPHERAL_BASE + 0x00001000)
#define IXP425_PMU_BASE		(IXP425_PERIPHERAL_BASE + 0x00002000)
#define IXP425_INTC_BASE	(IXP425_PERIPHERAL_BASE + 0x00003000)
#define IXP425_GPIO_BASE	(IXP425_PERIPHERAL_BASE + 0x00004000)
#define IXP425_TMR_BASE		(IXP425_PERIPHERAL_BASE + 0x00005000)
#define IXP425_NPEA_BASE	(IXP425_PERIPHERAL_BASE + 0x00006000)
#define IXP425_NPEB_BASE	(IXP425_PERIPHERAL_BASE + 0x00007000)
#define IXP425_NPEC_BASE	(IXP425_PERIPHERAL_BASE + 0x00008000)
#define IXP425_EthA_BASE	(IXP425_PERIPHERAL_BASE + 0x00009000)
#define IXP425_EthB_BASE	(IXP425_PERIPHERAL_BASE + 0x0000A000)
#define IXP425_USB_BASE		(IXP425_PERIPHERAL_BASE + 0x0000B000)
#define IXP425_DMA_BASE		(IXP425_PERIPHERAL_BASE + 0x0000F000)


/* PCI Memory Space */
#define IXP425_PCI_BASE		(0x48000000)
#define IXP425_PCI_SP_SIZE	(SZ_128M)


/* Expansion Bus 'lives' at either base1 or base 2 depending on the value of Exp Bus config registers.
 *  exp_cnfg0 : setting bit 31 of 0xC4000020 puts SDRAM at zero, and The expansion bus to IXP425_EXPANSION_BUS_BASE2
 */

#define IXP425_EXPANSION_BUS_BASE1	(0x00000000)
#define IXP425_EXPANSION_BUS_BASE2	(0x50000000)

#define IXP425_SDRAM_BASE		(0x00000000)
#define IXP425_SDRAM_BASE_ALT		(0x10000000)

#define IXP425_EXPANSION_BUS_CS0_BASE	(0x50000000)
#define IXP425_EXPANSION_BUS_CS1_BASE	(0x51000000)
#define IXP425_EXPANSION_BUS_CS2_BASE	(0x52000000)
#define IXP425_EXPANSION_BUS_CS3_BASE	(0x53000000)
#define IXP425_EXPANSION_BUS_CS4_BASE	(0x54000000)
#define IXP425_EXPANSION_BUS_CS5_BASE	(0x55000000)
#define IXP425_EXPANSION_BUS_CS6_BASE	(0x56000000)
#define IXP425_EXPANSION_BUS_CS7_BASE	(0x57000000)

/* The entire expansion bus addressable area is 128Meg, 16Meg 
 * for each of the CS regions. */
#define IXP425_EXPANSION_BUS_TOTAL_SIZE       (8 * SZ_16M)


/* Memory region ALIASES
 *
 * When operating in Little Endian XScale mode, we sometimes need to access certain
 * memory regions in BOTH Address Coherent and Data Coherent modes.
 * To achieve this, we create an alias for each memory region for which dual-coherency
 * mode access is required.
 *
 * The default base address will point to that memory space in Address Coherent mode.
 * The ALIAS address will point to the same memory space in Data Coherent mode.
 * We use reserved memory space for the alias regions.
 *
 * WARNING - These alias addresses MUST be 1 MByte aligned.
 * WARNING - Modifying these aliases will require manual modification
 *           of the ROM MMU translation table defined in romInit.s. 
 * See also sysLib.c where the coherency mode of each memory region is configured.
 * 
 * The following list contains the alias addresses required:
 */
#define IXP425_PERIPHERAL_LE_DC_VIRT           (IXP425_SDRAM_CONFIG_BASE + 0x100000)
#define IXP425_QMGR_LE_DC_VIRT                 (IXP425_SDRAM_CONFIG_BASE + 0x200000)
#define IXP425_EXP_CONFIG_LE_DC_VIRT           (IXP425_SDRAM_CONFIG_BASE + 0x300000)
#define IXP425_EXPANSION_BUS_BASE2_LE_DC_VIRT  (IXP425_SDRAM_CONFIG_BASE + 0x400000)

/* The "P-Bit" mask value, bit 9 in the MMU first level descripter is used to
 * switch between address and data coherency in XSCALE on a 1meg page basis
 * With the bit set the region is set to data coherency. 
 * N.B. The expansion config base register EXP_CFG1_BYTE_SWAP_EN (bit 8) must also
 *      be set for the P-Bit to have any affect */
#define P_BIT_SET_MASK    (0x200)

/*****************************************************************
 * SDRAM Controller Address 
 *
 *****************************************************************/
#define IXP425_SDRAM_CONFIG			( IXP425_SDRAM_CONFIG_BASE + 0x00000000)
#define IXP425_SDRAM_REFRESH			( IXP425_SDRAM_CONFIG_BASE + 0x00000004)
#define IXP425_SDRAM_INSTRUCTION		( IXP425_SDRAM_CONFIG_BASE + 0x00000008)

/* Bit definitions  - IXP425_SDRAM_CONFIG */

#define IXP425_SDRAM_CAS_3CLKS		(0x0008)
#define IXP425_SDRAM_CAS_2CLKS		(0x0000)

#define IXP425_SDRAM_32Meg_2Chip	(0x0000)
#define IXP425_SDRAM_64Meg_4Chip	(0x0001)
#define IXP425_SDRAM_64Meg_2Chip	(0x0002)
#define IXP425_SDRAM_128Meg_4Chip	(0x0003)
#define IXP425_SDRAM_128Meg_2Chip	(0x0004)
#define IXP425_SDRAM_256Meg_4Chip	(0x0005)

/* Bit definitions  - IXP425_SDRAM_REFRESH */
#define IXP425_SDRAM_REFRESH_DISABLE 	(0x0)

/* Bit definitions  - IXP425_SDRAM_INSTRUCTION */
#define IXP425_SDRAM_IR_MODE_SET_CAS2_CMD 	(0x0000)
#define IXP425_SDRAM_IR_MODE_SET_CAS3_CMD 	(0x0001)
#define IXP425_SDRAM_IR_PRECHARGE_ALL_CMD 	(0x0002)
#define IXP425_SDRAM_IR_NOP_CMD 		(0x0003)
#define IXP425_SDRAM_IR_AUTOREFRESH_CMD 	(0x0004)
#define IXP425_SDRAM_IR_BURST_TERMINATE_CMD	(0x0005)
#define IXP425_SDRAM_IR_NORMAL_OPERATION_CMD	(0x0006)







/******************************************************************

  Interrupt Controller Register Definitions.

******************************************************************/

#include <ixp425IntrCtl.h>

/******************************************************************

  Operating System Timer Register Definitions.

******************************************************************/

#define IXP425_OSTS	( IXP425_TMR_BASE + 0x0 )  /* Continious TimeStamp Reg. */
#define IXP425_OST1	( IXP425_TMR_BASE + 0x4 )   /* Timer 1 Timestamp Reg. */
#define IXP425_OSRT1	( IXP425_TMR_BASE + 0x8 )   /* Timer 1 Reload Reg. */
#define IXP425_OST2	( IXP425_TMR_BASE + 0xC )   /* Timer 2 Timestamp Reg. */
#define IXP425_OSRT2	( IXP425_TMR_BASE + 0x10 )  /* Timer 2 Reload Reg. */
#define IXP425_OSWT	( IXP425_TMR_BASE + 0x14 )  /* Watchdog Timer Reg. */
#define IXP425_OSWE	( IXP425_TMR_BASE + 0x18 )  /* Watchdog Enable Reg. */
#define IXP425_OSWK	( IXP425_TMR_BASE + 0x1C )  /* Watchdog Key Reg. */
#define IXP425_OSST	( IXP425_TMR_BASE + 0x20 )  /* Timer Status Reg. */


/* Watchdog timer defines */
#define IXP425_OSW_RESET_ENABLE                (BIT(0))
#define IXP425_OSW_INTERRUPT_ENABLE            (BIT(1))
#define IXP425_OSW_COUNT_ENABLE                (BIT(2))
#define IXP425_OSW_ENABLE_REG_WRITE_KEY_VALUE  (0x482E) /* Enables writes to the Watchdog
							 * and the Watchdog key reg */
#define IXP425_OST_ENABLE              BIT(0)
#define IXP425_OST_ONE_SHOT            BIT(1)
#define IXP425_OST_RELOAD_MASK         (0x3)    /* Low order bits of
						 * reload value
						 * ignored */
#define IXP425_OST_DISABLED            (0x0)

#define IXP425_OSST_TIMER_1_PEND       BIT(0)
#define IXP425_OSST_TIMER_2_PEND       BIT(1)
#define IXP425_OSST_TIMER_TS_PEND      BIT(2)
#define IXP425_OSST_TIMER_WDOG_PEND    BIT(3)
#define IXP425_OSST_TIMER_WARM_RESET   BIT(4)

#define IXP425_OSST_TICKS_PER_SECOND	60
#define IXP425_OSST_ROLLOVER		333330 /* at 66Mhz clock = 60 ticks per sec. */

/* 
 * UART Register Definitions , Offsets only as there are 2 UARTS.
 *   IXP425_UART1_BASE , IXP425_UART2_BASE.
 */

#undef  UART_NO_RX_INTERRUPT

#define IXP425_NUM_UARTS (2)
#define IXP425_UART_XTAL ( 14745600)
#define IXP425_UART_REG_DELTA (4) 	/* Uart registers are spread out by 4 bytes */

#define IXP425_UART_RBR_OFFSET (0x00)	/* Receive Buffer Register - read only */
#define IXP425_UART_THR_OFFSET (0x00)	/* Transmit Hold Register(write buffer) - write only */
#define IXP425_UART_IER_OFFSET (0x04)	/* Interrupt Enable */
#define IXP425_UART_IIR_OFFSET (0x08)	/* Interrupt ID (read only)  */
#define IXP425_UART_FCR_OFFSET (0x08)	/* FIFO Control - (write only)  */
#define IXP425_UART_LCR_OFFSET (0x0C)	/* Line Control - r/w  */
#define IXP425_UART_MCR_OFFSET (0x10)	/* Modem Control  - r/w */
#define IXP425_UART_LSR_OFFSET (0x14)	/* Line Status - read only  */
#define IXP425_UART_MSR_OFFSET (0x18)	/* Modem Status - read only  */
#define IXP425_UART_SPR_OFFSET (0x1C)	/* Scratch register r/w  */


/* Note The Divisor can only be written to with DLAB bit of the Line
 * Control register is set, Note: for changes of baud rate the device 
 * should be disabled to prevent the s/w from reading the devisor latch 
 * as data 
 */

#define IXP425_UART_DLL_OFFSET (0x00)	/* Divisor Latch LSB  */
#define IXP425_UART_DLH_OFFSET (0x04)	/* Divisor Latch MSB  */

/* UART BIT DEFINITIONS. */

/* Line control register */
#define IXP425_UART_LCR_WS_5_BIT 	(0) /* 5 bit character */
#define IXP425_UART_LCR_WS_6_BIT 	(1) /* 6 bit character */
#define IXP425_UART_LCR_WS_7_BIT 	(2) /* 7 bit character */
#define IXP425_UART_LCR_WS_8_BIT 	(3) /* 8 bit character */
#define IXP425_UART_LCR_STB_BIT 	BIT(2) /* 0 = 1 Stop Bit,
						  1 = 2 Stop Bits  */ 
#define IXP425_UART_LCR_PEN_BIT 	BIT(3) /* Parity Enabled */
#define IXP425_UART_LCR_EPS_BIT 	BIT(4) /* Even Parity Select - 1 for even parity, 0 for odd */
#define IXP425_UART_LCR_STKYP_BIT 	BIT(5) /* Sticky Parity */
#define IXP425_UART_LCR_SB_BIT 		BIT(6) /* Set Break */
#define IXP425_UART_LCR_DLAB_BIT 	BIT(7) /* DLAB - Divisor Latch Bit  */


/******************************************************************

  GPIO Register Definitions.
  [Only perform 32bit reads/writes]

******************************************************************/

#define IXP425_GPIO_GPOUTR	(IXP425_GPIO_BASE + 0x0000)
#define IXP425_GPIO_GPOER	(IXP425_GPIO_BASE + 0x0004)
#define IXP425_GPIO_GPINR	(IXP425_GPIO_BASE + 0x0008)
#define IXP425_GPIO_GPISR	(IXP425_GPIO_BASE + 0x000C)
#define IXP425_GPIO_GPIT1R	(IXP425_GPIO_BASE + 0x0010)
#define IXP425_GPIO_GPIT2R	(IXP425_GPIO_BASE + 0x0014)
#define IXP425_GPIO_GPCLKR	(IXP425_GPIO_BASE + 0x0018)
#define IXP425_GPIO_GPDBSELR	(IXP425_GPIO_BASE + 0x001C)

/*
 * Expansion Bus Controller registers.
 */

#define IXP425_EXP_CS0_REG		(IXP425_EXP_CONFIG_BASE + 0x00)
#define IXP425_EXP_CS1_REG		(IXP425_EXP_CONFIG_BASE + 0x04)
#define IXP425_EXP_CS2_REG		(IXP425_EXP_CONFIG_BASE + 0x08)
#define IXP425_EXP_CS3_REG		(IXP425_EXP_CONFIG_BASE + 0x0C)
#define IXP425_EXP_CS4_REG		(IXP425_EXP_CONFIG_BASE + 0x10)
#define IXP425_EXP_CS5_REG		(IXP425_EXP_CONFIG_BASE + 0x14)
#define IXP425_EXP_CS6_REG		(IXP425_EXP_CONFIG_BASE + 0x18)
#define IXP425_EXP_CS7_REG		(IXP425_EXP_CONFIG_BASE + 0x1C)

#define IXP425_EXP_CNFG0_REG_OFFSET     (0x20)
#define IXP425_EXP_CNFG1_REG_OFFSET     (0x24)
#define IXP425_EXP_CNFG2_REG_OFFSET     (0x28)
#define IXP425_EXP_CNFG3_REG_OFFSET     (0x2c)

#define IXP425_EXP_CNFG0		(IXP425_EXP_CONFIG_BASE + IXP425_EXP_CNFG0_REG_OFFSET)
#define IXP425_EXP_CNFG1		(IXP425_EXP_CONFIG_BASE + IXP425_EXP_CNFG1_REG_OFFSET)
#define IXP425_EXP_CNFG2		(IXP425_EXP_CONFIG_BASE + IXP425_EXP_CNFG2_REG_OFFSET)
#define IXP425_EXP_CNFG3		(IXP425_EXP_CONFIG_BASE + IXP425_EXP_CNFG3_REG_OFFSET)

/* When the EXP_CFG1_BYTE_SWAP_EN bit is set in the expansion bus 
 * config 1 register, the P-Bit can be used by the MMU to control address
 * and data coherency selection */
#define IXP425_EXP_CFG1_BYTE_SWAP_EN    (0x100) /* Bit 8 */

/*
 * Clock Speed Definitions.
 */

#define IXP425_PERIPHERAL_BUS_CLOCK (66) 


#ifdef __cplusplus
}
#endif

#endif /* ixp_ixp425.h */