rominit.s

ixp425 bsp for vxworks

	
init_dram:

/* Disable refresh Cycles */
	ldr	r9, L$LIXP425_SDRAM_REFRESH
	ldr	r0, L$LIXP425_SDRAM_REFRESH_DISABLE
	str	r0, [r9, #0]		/* Disable Refresh Cycle */

	DELAY	(0x4000, r0)

/* Issue a NOP Command to all SDRAM devices */
	ldr	r9, L$LIXP425_SDRAM_INSTRUCTION
	ldr	r0, L$LIXP425_SDRAM_IR_NOP_CMD
	str	r0, [r9, #0]		/* Issue NOP cmd to SDRAM */

	DELAY	(0x4000, r0)

	ldr	r9, L$LIXP425_SDRAM_REFRESH
	ldr	r0, L$LIXDP425_SDRAM_CONFIG_REFRESH_CNT
	str	r0, [r9, #0]		/* Set refresh value  */

	DELAY	(0x4000, r0)


/* Send a PrechargeAll Command to all SDRAM devices */
	ldr	r9, L$LIXP425_SDRAM_INSTRUCTION
	ldr	r0, L$LIXP425_SDRAM_IR_PRECHARGE_ALL_CMD
	str	r0, [r9, #0]		/* Precharge all */
	DELAY	(0x4000, r0)


/* Send 8 AutoRefresh Command. There should Trc cycles between every
 *  AutoRefresh. Trc = 70ns for devices used here,  */
	ldr	r9, L$LIXP425_SDRAM_INSTRUCTION
	ldr	r0, L$LIXP425_SDRAM_IR_AUTOREFRESH_CMD
	str	r0, [r9, #0]	/* Auto Refresh #1 */
	DELAY	(0x100, r0)
	str	r0, [r9, #0]	/* Auto Refresh #2 */
	DELAY	(0x100, r0)
	str	r0, [r9, #0]	/* Auto Refresh #3 */
	DELAY	(0x100, r0)
	str	r0, [r9, #0]	/* Auto Refresh #4 */
	DELAY	(0x100, r0)
	str	 r0, [r9, #0]	/* Auto Refresh #5 */
	DELAY	(0x100, r0)
	str	r0, [r9, #0]	/* Auto Refresh #6 */
	DELAY	(0x100, r0)
	str	r0, [r9, #0]	/* Auto Refresh #7 */
	DELAY	(0x100, r0)
	str	r0, [r9, #0]	/* Auto Refresh #8 */
	DELAY	(0x100, r0)

/* Send Mode Reg Set Cmd with CAS Latency 3 */
	ldr	r9, L$LIXP425_SDRAM_INSTRUCTION
	ldr	r0, L$LIXP425_SDRAM_IR_MODE_SET_CAS3_CMD
	str	r0, [r9, #0]	/* Send Mode Select Command */
	DELAY	(0x4000, r0)

	ldr	r9, L$LIXP425_SDRAM_INSTRUCTION
	ldr	r0, L$LIXP425_SDRAM_IR_NORMAL_OPERATION_CMD
	str	r0, [r9, #0x00000000]	/* Issue a Normal Operation command */


#endif /* INIT_SDRAM */

/*************** SDRAM Config Complete ***************************************/

	/* DebugOutVal INFO_CODE_9 */
	mov	r0, #0x0009
	bl	FUNC(SevenSegDisplay)


/* Enable Coprocessors access */

        ldr	r0, =0x001
        mcr	p15, 0, r0, c15, c1, 0

        mcr	p15, 0, r0, c7, c10, 4  /* Drain write/fill buffers */
	CPWAIT	(r0)			/* wait for the write to happen */
	CPWAIT	(r0)			/* wait for the write to happen */

/* Invalidate I-Cache, D-Cache, and BTB */
        mcr	p15, 0, r0, c7, c7, 0
	CPWAIT	(r0)			/* Wait */

/* Set the CS0 setting for Flash to optimum timings. */
	ldr	r0, L$LIXP425_EXP_CS0_REG
	ldr	r1, L$LIXDP425_FLASH_CS_DEFAULT
	str	r1, [r0]

	/* DebugOutVal INFO_CODE_C */
	mov	r0, #0x000c
	bl	FUNC(SevenSegDisplay)


/*** Enable Write Buffer Coalescing ***/

#if XSCALE_WB_COAL_ENABLE
	mcr	p15, 0, r0, c7, c10, 4  /* Drain write/fill buffers */
	CPWAIT	(r0)			/* wait for the write to happen */
	CPWAIT	(r0)			/* wait for the write to happen */

	mrc	p15, 0, r0, c1, c0, 1   /* Read Auxiliary Control Reg */
	and	r0, r0, #0xfffffffe    	/* Enable Coalescing */
	mcr	p15, 0, r0, c1, c0, 1   /* Write Auxiliary Control Reg */
	CPWAIT	(r0)			/* wait for the write to happen */

	NOP
	NOP
#endif

warm_start:
/* Disable Interrupts */
        MRS     r1, cpsr                /* get current status */
        ORR     r1, r1, #I_BIT | F_BIT  /* disable IRQ and FIQ */
        MSR     cpsr, r1

/* Interrupts Disabled */

        ldr     r0, L$LIXP425_ICMR	/* Zero-out Interrupt Mask */
        mov     r2, #0x0
        str     r2, [r0]

/* 3: Jump to here + New Flash Location. We could jump up to location in
 *    Flash, but we have already copied enough code to low ram to continue code
 *    execution from here */

	ldr	r0, =IXP425_EXPANSION_BUS_BASE2
        orr	r0, r0, pc
	mov	pc, r0

/* 4: Write to Expansion Bus controller to swap Flash & Ram */

	ldr	r0, L$LIXP425_EXP_CNFG0
	ldr	r1, [r0]
	and	r1, r1,#0x7FFFFFFF
	str	r1, [r0]

/* End of switch , should now be running in Flash in its relocated position.*/

	/* DebugOutVal INFO_CODE_D */
	mov	r0, #0x000d
	bl	FUNC(SevenSegDisplay)

/* Enable Coprocessors access */
        ldr     r0, =0x001
        mcr     p15, 0, r0, c15, c1, 0

        mcr     p15, 0, r0, c7, c10, 4	/* Drain write/fill buffers */
	CPWAIT	(r0)			/* wait for the write to happen */
	CPWAIT	(r0)			/* wait for the write to happen */

#ifdef ROM_ENABLES_MMU
/* Enable the MMU */
		
	/* Update the seven segment display */
	mov	r0, #0x00A1
	bl	FUNC(SevenSegDisplay)

	/* Invalidate the entire instruction cache */
        ldr     r0, =0x0
	mcr     p15, 0, r0, c7, c5, 0
	CPWAIT	(r0)
	
	/* Update the seven segment display */
	mov	r0, #0x00A2
	bl	FUNC(SevenSegDisplay)

	/* Set Translation Table Base */
	LDR	r0, L$_romL1PTable
        mcr     p15, 0, r0, c2, c0, 0	/* Set Translation Table Base Register*/
        CPWAIT	(r0)                    /* Wait */
	
	/* Update the seven segment display */
	mov	r0, #0x00A3
	bl	FUNC(SevenSegDisplay)

	/* Invalidate the Instruction and Data TLBs */
        ldr     r0, =0x0
	mcr     p15, 0, r0, c8, c7, 0
	CPWAIT	(r0)

	/* Update the seven segment display */
	mov	r0, #0x00A4
	bl	FUNC(SevenSegDisplay)
	
	/* Set Domain Access Control Register */
	mov	r0, #0xFFFFFFFF 	/* Set All 16 domains to mgr access*/
        mcr     p15, 0, r0, c3, c0, 0	/* Set Domain Permissions */
	CPWAIT	(r0)                    /* Wait */

	/* Update the seven segment display */
	mov	r0,  #0x00A5
	bl	FUNC(SevenSegDisplay)

	/* Enable LE Data coherence operation, no effect until MMU
	 * is enabled. */
	ldr	r0, L$LIXP425_EXP_CNFG1
	ldr	r1, [r0]
	orr	r1, r1, #IXP425_EXP_CFG1_BYTE_SWAP_EN
	str	r1, [r0]
	
	/* Update the seven segment display */
	mov	r0, #0x00A6
	bl	FUNC(SevenSegDisplay)

	/* Enable Data Cache */
        mrc     p15, 0, r0, c1, c0, 0   /* Read Control Reg */
        orr     r0, r0, #0x00000004     /* Enable Data Cache */
        mcr     p15, 0, r0, c1, c0, 0   /* Write Back */
	CPWAIT	(r0)			/* Wait */

	/* Update the seven segment display */
	mov	r0, #0x00A7
	bl	FUNC(SevenSegDisplay)

	/* Enable Instruction Cache */
        mrc     p15, 0, r0, c1, c0, 0   /* Read Control Register*/
        orr     r0, r0, #0x1000         /* Set I-Cache bit */
        mcr     p15, 0, r0, c1, c0, 0   /* Write Back Control Register */
	CPWAIT	(r0)			/* Wait */

	/* Update the seven segment display */
	mov	r0, #0x00A8
	bl	FUNC(SevenSegDisplay)

	/* Turn on the MMU - At this stage we are still executing from ROM
	 * so we will still be in address coherency mode after the MMU 
	 * switches on */
	mrc     p15, 0, r9, c1, c0, 0  /* Get CP reg 15 value into r1 */
	orr     r9, r9, #0x1           /* Set Bit 0 of CP15 register 1 */
	mcr     p15, 0, r9, c1, c0, 0  /* Save new CP15 Reg 1 value */
	CPWAIT	(r0)                   /* wait for it */

	/* Update the seven segment display */
	mov	r0, #0x00A9
	bl	FUNC(SevenSegDisplay)
		
#endif /* ROM_ENABLES_MMU was defined */

/* Enable Branch Target Buffer */
        mrc     p15, 0, r0, c1, c0, 0   /* Read Control Reg */
        orr     r0, r0, #0x00000800	/* Enable BTB */
        mcr     p15, 0, r0, c1, c0, 0   /* Write Back the Control Reg */
	CPWAIT	(r0)			/* Wait */

/* Enable trap for mis-aligned data */
        mrc     p15, 0, r0, c1, c0, 0   /* Read Control Reg */
        orr     r0, r0, #0x00000002	/* set alignment trap bit */
        mcr     p15, 0, r0, c1, c0, 0   /* Write Back the Control Reg */
	CPWAIT	(r0)			/* Wait */

/******************************************************************************/
/******************************************************************************/

	/* DebugOutVal INFO_CODE_E */
	mov	r0, #0x000e
	bl	FUNC(SevenSegDisplay)


vxWorks_boot:

/*  Now jump to the code that starts the whole vxWorks boot process */
	mov	r0, r8
	ldr	sp, L$STACK_ADDR
	ldr	pc, L$StrtInFlash

/******************************************************************************/
/******************************************************************************/

UARTVString:

/* Do nothing as byte reads from flash not allowed */
	mov	pc, lr
        ldr     r10, =IXP425_UART1_BASE

UARTNextChar:
        ldrb    r1, [r0], #1
        teq     r1, #0
        beq     URATTxDone


        /* UARTTextOut     r10, r1, r2 */
        and     r1, r1, #0xff

/* Modified, don't even check if there is room in the transfer fifo just do it.
 * TODO : remove later, on real card */
/*
        ldr     r10, =IXP425_UART1_BASE
        ldr     r2, [r10, #UART_LineStatus]
        TST     r2. #UARTLSR_TXHoldingEmpty
        BEQ     10b
*/
        strb	r1, [r10, #UART_Transmit]	

/* Start-  Included to slow down writes to simultor : TODO: Remove later */
	DELAY	(0x200, r3)
/*End-  Included to slow down writes to simultor : TODO: Remove later */

        B       UARTNextChar

URATTxDone:
        mov     r1, #13
        /* UARTTx          r10, r1, r2 */
        mov     r1, #10
        strb    r1, [r10, #UART_Transmit]
        /* UARTTx          r10, r1, r2 */
        strb    r1, [r10, #UART_Transmit]
	mov	pc, lr

/* Better not to use r0, r1, r2 and r10s. Uses r0, r10 */
UARTStart:
        ldr     r10, =IXP425_UART1_BASE
	ldr	r0, =UART_DMABodgeDelay

UARTDelay:
	subs	r0, r0, #1
	bne	UARTDelay

/* Enable access to divisor registers */

	mov	r0, #UARTLCR_DivisorLatchAccess
	strb	r0, [r10, #UART_LineControl]

	ldr	r0, =UART_DMABodgeDelay

UARTDelay1:
	subs	r0, r0, #1
	bne	UARTDelay1

        /* select baud rate */
	ldr	r0, =BaudRateDivisor_9600
	strb	r0, [r10, #UART_DivisorLatchLSB]
	mov	r0, r0, LSR #8
	strb	r0, [r10, #UART_DivisorLatchMSB]

	/* 8 data, 1 stop, no parity */
	mov	r0, #UARTLCR_CharLength8 | UARTLCR_StopBits1

	/* also disable access to divisor regs */
	strb	r0, [r10, #UART_LineControl]

	/* no irqs , but enable the UART on IXP425 */
	mov	r0, #0x40
	strb	r0, [r10, #UART_InterruptEnable]

	mov     r0, #UARTFCR_Enable
	strb     r0, [r10, #UART_FIFOControl]
	/* turn fifos on */
	mov     r0, #UARTFCR_RXReset | ARTFCR_TXReset | UARTFCR_Mode0RXRDYTXRDY | UARTFCR_RXTrigger1
	strb     r0, [r10, #UART_FIFOControl]

	/* make DTR active, RTS inactive, stop other end */
	mov	r0, #UARTMCR_DTRActive
	strb	r0, [r10, #UART_ModemControl]

	mov	pc, lr

/******************************************************************************/
/******************************************************************************/

_ARM_FUNCTION(SevenSegDisplay)
#ifdef INCLUDE_IXDP425_LED_DEBUG
        ldr     r6, L$LED_DISPLAY
        strh    r0, [r6]
#endif
        mov     pc, lr

/******************************************************************************/
/******************************************************************************/

#ifdef _DIAB_TOOL
        .ltorg
#endif  /* _DIAB_TOOL */
	.align 4

#ifdef ROM_ENABLES_MMU
/* The MMU translation table address needs to be a physical address */
L$_romL1PTable:         .long   ROM_TEXT_ADRS + FUNC(romL1PTable) - FUNC(romInit)
#endif

L$LIXP425_ICMR:         .long   IXP425_ICMR
L$LIXP425_EXP_CNFG0:    .long   IXP425_EXP_CNFG0
L$LIXP425_EXP_CNFG1:    .long   IXP425_EXP_CNFG1

L$StrtInRam:		.long   FUNC(romStart) - FUNC(romInit)

L$StrtInFlash:		.long   ROM_TEXT_ADRS + FUNC(romStart) - FUNC(romInit)

L$STACK_ADDR:		.long	STACK_ADRS

L$FlashDramSwapSize:	.long  BOOT_ROM_RELOCATE_SIZE

L$LIXP425_EXP_CS0_REG:				.long	IXP425_EXP_CS0_REG
L$LIXDP425_FLASH_CS_DEFAULT:			.long	IXDP425_FLASH_CS_DEFAULT

/* SDRAM Literals */
L$LIXP425_SDRAM_CONFIG_BASE:			.long	IXP425_SDRAM_CONFIG_BASE
L$LSDRAM_CONFIG_32MEG:				.long	SDRAM_CONFIG_32MEG
L$LSDRAM_CONFIG_64MEG:				.long   SDRAM_CONFIG_64MEG
L$LSDRAM_CONFIG_128MEG:				.long	SDRAM_CONFIG_128MEG
L$LSDRAM_CONFIG_256MEG:				.long	SDRAM_CONFIG_256MEG
L$LIXP425_SDRAM_CONFIG:				.long   IXP425_SDRAM_CONFIG

L$LIXP425_SDRAM_REFRESH: 			.long 	IXP425_SDRAM_REFRESH
L$LIXP425_SDRAM_REFRESH_DISABLE:		.long 	IXP425_SDRAM_REFRESH_DISABLE
L$LIXP425_SDRAM_INSTRUCTION:			.long   IXP425_SDRAM_INSTRUCTION
L$LIXP425_SDRAM_IR_NOP_CMD:			.long   IXP425_SDRAM_IR_NOP_CMD
L$LIXDP425_SDRAM_CONFIG_REFRESH_CNT:		.long   IXDP425_SDRAM_CONFIG_REFRESH_CNT
L$LIXP425_SDRAM_IR_PRECHARGE_ALL_CMD:		.long   IXP425_SDRAM_IR_PRECHARGE_ALL_CMD
L$LIXP425_SDRAM_IR_AUTOREFRESH_CMD:		.long   IXP425_SDRAM_IR_AUTOREFRESH_CMD
L$LIXP425_SDRAM_IR_MODE_SET_CAS3_CMD:		.long	IXP425_SDRAM_IR_MODE_SET_CAS3_CMD
L$LIXP425_SDRAM_IR_NORMAL_OPERATION_CMD:	.long   IXP425_SDRAM_IR_NORMAL_OPERATION_CMD


/* DebugOutInitLiteral */
L$CS2_REG:	.long 0xc4000008
L$CS2_VAL:	.long 0xBFFF0002

L$LED_DISPLAY:	.long IXDP425_7SEG_BASE
		
/* MMU Translation Table statically defined in ROM and used during bootrom
 * bring up. The application code transistions to using its own translation 
 * table.
 * Each entry corresponds to a megabyte of virtual address space and is a 
 * section descriptor, containing the physical address for the megabyte of 
 * virtual address space.
 *
 * A Level 1 page table must be 16 kilobyte-aligned WHEN IT IS IN THE FLASH 
 * DEVICE.
 * Please refer to target.nr for a diagram of the IXP425 memory map
 * N.B. There _MUST_ not be any empty addressable regions in the table, i.e
 *      the count variable must increment sequentially from 0 to 0xfff. If 
 *      it does not then table entries _will_ be in the wrong position! */
#ifdef ROM_ENABLES_MMU