target.nr

ixp425 bsp for vxworks

The IXDP425 board is equipped with 133MHz SDRAM - 256 Mbytes total (2 Banks, 4 chips,
 512Mbit) The devices used shall be Micron MT48LC16M16A2TG-7E16Meg x 16bits.143Mhz Grade, 
Cas Latency (Read) = 3. www.micronsemi.com/datasheets/sdramds.html

.SS "Interrupts"
All interrupts are handled via the internal interrupt controller module.

Interrupt connections, enabling, and disabling are performed using the 
standard intArchLib routines.  The interrupt controller driver is 
provided in ixp425IntrCtl.c.

.SS "IXDP425 Memory Map"
.CS
Resource					Base Address
=========================================================================
SDRAM*			       			0x00000000**
SDRAM Alias 1					0x10000000
SDRAM Alias 2					0x20000000
SDRAM Alias 3					0x30000000
PCI space    					0x48000000
Flash/Expansion Bus				0x50000000**
Queue Manager					0x60000000
PCI controller					0xc0000000
Expansion Bus Config				0xc4000000

Peripheral Base
   |-->	UART1					0xc8000000
   |-->	UART2					0xc8001000
   |-->	PMU					0xc8002000
   |-->	Interrupt Controller			0xc8003000
   |-->	GPIO					0xc8004000
   |-->	Timer					0xc8005000
   |-->	WAN/HSS    				0xc8006000
   |-->	Ethernet     A				0xc8007000
   |-->	Ethernet     B				0xc8008000
   |-->	Ethernet MAC A LXT971A (port1)		0xc8009000
   |-->	Ethernet MAC B LXT971A (port2)		0xc800a000
   |-->	USB Controller				0xc800b000

SDRAM Controller				0xcc000000

Little Endian Data Coherent Virtual Maps***	Virtual    --> Real Addr
   |						----------     ----------
   |-->	Peripheral Base (LE DC VIRT)		0xcc100000 --> 0xc8000000
   |-->	QMgr Base (LE DC VIRT)			0xcc200000 --> 0x60000000
   |-->	Exp Bus Config (LE DC VIRT)		0xcc300000 --> 0xc4000000
   |-->	Flash/Expansion Bus Base (LE DC VIRT)	0xcc400000 --> 0x50000000

.CE

*Note:	When compiled for little endian mode SDRAM gets configured to be
	data coherent.
**Note:	Flash initially resides at 0x00000000 and moves up to 0x50000000
	after bootup.
***Note:The data coherent virtual maps are used by the Intel IXP425 software
	when it is configured in little endian mode. Compile time switches
	determine whether the real base addresses or the data coherent virtual
	base addresses are used by the various IXP425 components. However, even
	when in little endian mode the BSP itself does not make memory accesses
	to these virtual regions.

.SS "Serial Configuration"
There are two serial ports on the IXDP425 evaluation board.
The default configuration is 9600 baud, 8 data bits, no parity, 1 stop
bit. By default UART 1 is used as the VxWorks console port, and UART 0 is
used as the serial debug port for the WDB agent, or is available to the
application if SERIAL_DEBUG is not defined.
UART 1 is capable of supporting rates as high as 231K baud, while UART
0 (High Speed Uart) is capable of supporting rates as high as 926.1K baud. 

.SS "SCSI Configuration"
The IXDP425 development board does not have any on-card SCSI devices.  
This BSP does not support SCSI.

.SS "Network Configuration"
The IXDP425 evaluation board provides two high speed ethernet ports. 
The two high speed ethernet ports are LXT791A PHYS connected
to two MII ports and run at 10/100Mbit/s each.

Each PHY has two LEDs on its RJ-45 connector. The first LED indicates link status
and activity. This LED is illuminated (solid) when valid link pulses are received 
and no other activity is present.  The LED flashes when a valid link exists and data 
is being received or transmitted.  The 2nd LED indicates the link speed as determined 
during auto-negotiation (or link pulse inspection). 

.SS "VME Access"
The IXP425 development board does not have VME bus support.

.SS "PCI Access"
PCI v2.2 bus: 32-bit Address/Data bus. Capable of running at 33 and 66MHz.  
A built-in arbiter supports up to 4 external bus masters.
The IXDP425 BSP supports, and has been tested with PCI Ethernet cards
containing the Intel 8255X Ethernet network device. This is a fast Ethernet
controller capable of operating at 10Base-T and 100Base-T.

.SS "7-Segment Hex Display"
The Seven segment display is used to track boot progress. The displayed values have
the following meanings

.CS
0001 - Cold Boot entry
0002 - Debug uart initialized
0003 - reserved
0004 - reserved
0005 - reserved
0006 - reserved
0007 - Initializing SDRAM
0008 - reserved
0009 - SDRAM Initialization complete
                 Starting basic hw config
000C - warm start entry point, relocate flash
000D - enable MMU, optionally in Big endian, required in little endian.
000E - Starting vxWorks boot

0010 - Starting sysHwInit0
0011 - Finished cachelibinit, starting mmu init
0012 - Finished mmuinit, starting autosize init
0013 - finished autosize and sysHwInit0
0014 - starting sysHwInit
0015 - finished disabling interrupts,starting sysSerialHwInit
0016 - Finished sysSerialHwInit, starting sysPciInit (if PCI is enabled)
0017 - finished sysPciInit, starting sysPciAssignAddrs
0018 - finished sysPciAssignAddrs, starting sysEnableIRQMasks
0019 - finished sysEnableIRQMasks, and finished sysHwInit

0020 - sysHwInit2 begin, intLibInit started
0021 - intLibInit returned, starting ixp425IntDevInit
0022 - ixp425IntDevInit finished, starting sysSerialHwInit2
0023 - finished sysSerialHwInit2, starting sysPciIntConnect
0024 - finished sysPciIntConnect, starting sysPciIntEnable
0025 - finished sysPciIntEnable, starting sysLanPciInit
0026 - finished sysLanPciInit, starting ixdp425EthEndMuxInit (if supported)
0027 - finished all of sysHwInit2
.CE

.SS "BOOT DEVICES"
Supported boot devices are:
.CS
'fei' - 10/100BaseT PCI Ethernet  
'ixe' - 10/100BaseT Intel in chip Ethernet
.CE

.SH "SPECIAL CONSIDERATIONS"

.SS "Cache/MMU considerations"
The extra state VM_STATE_CACHEABLE_MINICACHE is available on the
IXP425. Setting pages to this state using
vmStateSet() will result in those pages being cached in the
mini-cache, and not in the main data cache.  Calling
cacheInvalidate(DATA_CACHE, ENTIRE_CACHE) will also invalidate the
mini-cache, but in all other aspects, no support is provided for
the mini-cache, and the user is entirely responsible for ensuring
cache coherency.

.SS "Timestamp support"
The IXDP425 BSP supports a system clock timer through hardware
timer 1. The timestamp clock is supported through the free running
up-timer.

.bS
              _________       _________         __________
hardware      GP TIMER0       GP TIMER1         Time-Stamp
clock         _________       _________         __________
                  |               |                 |
interface         -          -------------          -
                  |            |       |            |
                  |            |       |            |
software        _______   _________ ________    ____________
clock(s)        sysClk    sysAuxClk ixpAuxClk	timeStampClk
                -------   --------- ---------	------------

.bE


.SS "sysAuxClk and ixpAuxClk Polling Timers"
The IXDP425 BSP shares the hardware timer1 between the user's
auxiliary clock and an ethernet polling system that is typically used
for high bandwidth applications.

sysAuxClk functionality is available
to the user as specified my the vxWorks guidelines.  Mimicking the sysAuxClk,
there is an ixp BSP specific auxClk set of functions with the prefix ixpAuxClk.
Because these two subsystems share a clock a restriction has been made such
that one clock frequency must be a multiple of the other frequency.  If this
restriction is violated, the functions sysAuxClkRateSet() and
ixpAuxClkRateSet() will return ERROR.

To use the driver in interrupt mode, INCLUDE_IXETHACC_POLL_MODE should
be removed from the default configuration.  If interrupt mode is used,
then the auxClk is not shared and the above restrictions do not apply.

.SS "Divide by Zero Exception"
The ARM architecture does not provide for an integer divide by zero
exception.  Consequently, no exception is generated when an integer
divide by zero operation is performed programmatically.

.SS RFC 2233 SNMP MIB Support

In the default configuration this BSP fully supports RFC 2233 SNMP MIB
capabilities.  With this feature enabled there is a slight degradation
of ethernet throughput packet rate performance.  RFC 2233 may be
disabled by undefining INCLUDE_RFC_2233 in the file config.h.  Old
style RFC 1213 support will then be enabled.

Unfortunately, due to the overall design of the ixEthAccEnd driver and
underlying NPE functionality, if RFC 2233 is disabled some of the
statistics will be reported incorrectly.  This will be most evident in
the little endian version of the driver.

.SS "Known limitations/problems"

Console Shell (INCLUDE_SHELL) doesn't restart when telnet session disconnects.
        (Target Shell still works)

Reset switch does not work if visionProbe is connected and visionClick has been running.

Intel Ethernet devices do not provide support for polled mode. This means WDB will
not work with the system suspended.

.SS "BOARD LAYOUT"
The diagram below shows the board layout for the IXDP425 Development Board
containing the peripherals.
.bS

  _______________________________________________________________________________
 |                                                                               |
 |                                            +-------------------------------+  |
 |                                            | ---------- PCI SLOT --------- |  |
 |                     +---+ +---+            +-------------------------------+  |
 |  +--------------\   |   | |   |  J                                            |
 |  |              |   |   | |   | :P         +-------------------------------+  |
 |  |              |   |   | |   |  5         | ---------- PCI SLOT --------- |  |
 |  |              |   +---+ +---+            +-------------------------------+  |
 |  |    IXP425    |     SDRAM   5                                               |
 |  |              |   +---+ +---+            +-------------------------------+  |
 |  |              |   |   | |   |            | ---------- PCI SLOT --------- |  |
 |  |              |   |   | |   |            +-------------------------------+  |
 |  +--------------+   |   | |   |                                               |
 |  ._.  . .           +---+ +---+            +-------------------------------+  |
 | G._. G. .           JP9                    | ---------- PCI SLOT --------- |  |
 | P._. P. .      JP10  :           J11       +-------------------------------+  |
 | I._. I. .        :       +- # #  :|:                             _.. JP3    : |
 | O._. O. .               G+-                1.-.2 +--------------------------+ |
 |  ._.  . .     #         P+- # #             .-.  |                          | |  
 | H._. H. . +-----------+ 1+-                 . .  |                          | |  
 | E._. E. . |           | 5+- # #             . .  |                          | |  
 | A._. A. . |           |  +-                 . .  |                          | |  
 | D._. D. . |  FLASH    |  +- # #           J . .  |                          | |  
 | E._. E. . |           |  +-               8 . .  |                          | |  
 | R._. R. . |           |     # #             . .  |                          | |
 |  ._.  . . +-----------+  +-                 . .  |                          | |
 | A._. B. .    JP11       G+- # #             . .  |                          | |
 |  ._.          .._       P+-                 . .  |                          | |
 |  ._.   JP12             0+- # #           23. .24|                          | |
 |        _..              7+-                      |                          | |
 |                          +- # #            1.-.2 |  ++     POWER            | |
 |                          +-                 .-.  |  ||     MODULE           | |
 |                          +-                 .-.  |  ||                      | |
 |                                             . .  |  ||                      | |
 |+___________________+  +-------+             . .  |  ||                      | |
 ||                   |  |  LED  |             . .  |  ||                      | |
 ||                   |  |12 - 15|  +--+       . .  |  ||                      | |
 || +---------------+ |  +-------+  |J |       . .  |  ||                      | |
 || |               | |             |T |+--+   . .  |  ||                      | |
 || +---------------+ |  +-------+  |A ||B | J . .  |  ||                      | |
 ||                   |  |  LED  |  |G ||S | 9 . .  |  ||                      | |
 || U        +------+ |  | 8 - 11|  |  ||C |   . .  |  ||                      | |
 || T        |      | |  +-------+  |I ||A |   . .  |  ++                      | |
 || O        +------+ |             |C ||N |   . .  |                          | |
 || P                 |  +-------+  |E |+--+   . .  |                          | |
 || I                 |  |  LED  |  +--+       . .  |                          | |
 || A                 |  | 4 - 7 |             . .  |                          | |
 ||                   |  +-------+             . .  |                          | |
 || 2                 |                        . .  |                          | |
 ||                   |  +-------+      JP4    . .  |                          | |
 || M                 |  |  LED  |       :     . .  |                          | |
 || O                 |  | 0 - 3 |           43. .44|                          | |
 || D                 |  +-------+                  +--------------------------+ |
 || U                 |    : JP7                                                 |
 || L                 |+---------------------++---------------------+     vxWorks|
 || E                 ||                     ||                     |     Console|
 ||                   || +-----------------+ || +-----------------+ |      ______|
 || : JP13            || |                 | || |                 | |    P| SLOW |
 ||                   || +-----------------+ || +-----------------+ |    1|SERIAL|
 ||                   ||                     ||                     |     | PORT |
 ||                   || E                   || E                   | :   |______|
 ||                   || T                   || T                   | J          |
 ||                   || H                   || H                   | P    ______|
 ||                   || E                   || E                   | 2   | FAST |
 ||                   || R                   || R                   |    P|SERIAL|
 ||                   || N                   || N                   |    2| PORT |
 ||                   || E                   || E                   |     |______|
 ||                   || T                   || T                   |            |
 ||                   ||                     ||                     |          # |
 ||                   || 0                   || 1                   |          # |
 ||                   ||                     ||                     |          # |
 ||                   ||                     ||                     |          # |
 ||                   ||                     ||                     | +-----+  # |
 ||                   ||                     ||                     | | USB |  # |
 ||                   ||                     ||                     | | PORT| R  |
 ||___________________||_____________________||_____________________|_|_____|____|
.bE

.SH "See Also"
.tG "Getting Started,"
.pG "Configuration."

.SH "BIBLIOGRAPHY"
.I "Intel IXP425 I/O Companion Chip Developer's Manual",
.I "Intel IXP425 I/O Companion Chip Datasheet",
.I "Intel XScale Microarchitecture, Programmers Reference Manual",
.I "GNUPro Toolkit Documentation",