📄 syslib.c
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#endif /* INCLUDE_MMU */ }/********************************************************************************* sysHwInit - initialise the CPU board hardware** This routine initialises various features of the hardware.* Normally, it is called from usrInit() in usrConfig.c.** NOTE: This routine should not be called directly by the user.** RETURNS: N/A*/void sysHwInit (void) { int i; int dcacheStatus; /*store the Board rev read from the CPLD register*/ boardRev = (*((volatile UINT32 *) (CPLD_REV)) & 0xf0) >> 4; /*Get the system clock freq from the CPLD registers*/ getXtalFreq(); /*Initialize timer1 to be used in polled mode for all the delays*/ ixp2400Timer1Init(ixp2400XtalFreq); /* Call back from the kernel for Interrupt stack setup */ _func_armIntStackSplit = sysIntStackSplit; /*read the strap options register*/ IXP2400_REG_READ(IXP2400_STRAP_OPTIONS,strapOptionsVal); /*read the offset in flash where vxworks resides in case of booting thru BM *this is used in case of single flash, to get the source addr from where * the image has to be downloaded. */ if(sysStartType & BOOT_THRU_BM){ IXP2400_REG_READ(VXWORKS_TEXT_ADDR_LOC,vxWorksTextAddr); if(vxWorksTextAddr >= IXP2400_FLASH_BASE) vxWorksTextAddr = vxWorksTextAddr - IXP2400_FLASH_BASE; IXP2400_REG_WRITE(0xca001000,vxWorksTextAddr); } else vxWorksTextAddr =0; /* Set Slowport to 32 bit Read mode*/ IXP2400_REG_WRITE(IXP2400_SP_FRM,USE_32_BIT_DATA); /*save the Slowport configuration needed by CPLD CSRs*/ ixdp2400SPCfgSave(&spCfgCpld); /*initialise SRAM*/ dcacheStatus = (getCP15() & 0x04); if(dcacheStatus != 0) { dcacheSync(); dcacheOff(); } for(i = 0; i < MAX_QDR_CHANNEL; i++) { sysLEDDisplay('S', 'R', 'A','M'); ixdp2400SRAMInit(i, 0, 0, 0); } if(dcacheStatus != 0) dcacheOn(); /* Initialize sysPhysMemDescNumEnt */ while (sysPhysMemDesc[sysPhysMemDescNumEnt-1].len == 0) sysPhysMemDescNumEnt--;#if defined (INCLUDE_SERIAL) /* initialise the serial devices */ sysSerialHwInit ();#endif#if defined (INCLUDE_PCI) /* Initialize PCI driver library */ if (pciIomapLibInit (PCI_CONFIG0_BASE, PCI_CONFIG1_BASE) != OK) sysToMonitor(BOOT_NO_AUTOBOOT);#endif IXP2400_REG_WRITE(IXP2400_IRQ_ENABLE_CLR_REG, 0xFFFFFFFF); sysLEDDisplay('S', 'H', 'W','1'); }/********************************************************************************* sysHwInit2 - additional system configuration and initialisation** This routine connects system interrupts and does any additional* configuration necessary.** RETURNS: N/A** NOMANUAL*/void sysHwInit2 (void) { FAST int locKey; sysLEDDisplay('S', 'Y', 'S','2'); /* Allocate vector table and init handlers */ intLibInit (IXP2400_INT_NUM_LEVELS, IXP2400_INT_MAX_LEVELS, IXP2400_INT_MODE); sysLEDDisplay('I', 'N', 'T','R'); /* initialise the interrupt controller */ ixp2400IntDevInit ();#if defined (INCLUDE_SERIAL) /* connect serial interrupt */ sysSerialHwInit2 ();#endif#if defined(INCLUDE_MMU_BASIC) || defined(INCLUDE_MMU_FULL) /* These need to be set up for the case of a bootROM image * where the standard libraries do not set these values, but * the ethernet controller needs them. */ cacheDmaFuncs.virtToPhysRtn = (FUNCPTR) sysVirtToPhys; cacheDmaFuncs.physToVirtRtn = (FUNCPTR) sysPhysToVirt;#endif if(strapOptionsVal & CFG_PCI_BOOT_HOST) { /*Initialize i2c interface*/ i2c_init0(); sysLEDDisplay('I', '2', 'C',' '); /*copy config data from i2c EEPROM to Master's scratch pad memory. * for slave it will be done in sysInitSlave */ if(!(sysStartType & BOOT_THRU_BM)) { sysCFGDATAcopy(); } }#if defined (INCLUDE_PCI) /* initialize PCI unit */ if (!(!(strapOptionsVal & CFG_PCI_BOOT_HOST) && !(sysStartType & BOOT_COLD))) { sysLEDDisplay('P', 'C', 'I', ' '); sysPciInit(); }/* end of if */ /*The Slave has to wait for the master to copy Config data*/ if(!isNPUMaster()) { int counter = 0; while(pBoardCfgData->config_valid != CONFIG_DATA_VALID) { counter++; delayUSec(1000); if(counter > 2000) break; } }#if defined (AUTO_PCI_CONFIG) if(strapOptionsVal & CFG_PCI_BOOT_HOST) { /* assign address only on master */ sysPciAssignAddrs(); sysLEDDisplay('P', 'C', 'I','2'); sysInitSlave(); }#endif sysLEDDisplay('N', 'I', 'C','I'); sysLanPciInit(); #endif /* INCLUDE_PCI */#if defined (INCLUDE_PCI) intConnect((void*)INT_VEC_PIL, pciInt, INT_VEC_PIL); intEnable(INT_VEC_PIL); locKey = intLock(); /* enable pci interrupts */ IXP2400_REG_WRITE(IXP2400_PCI_XSCALE_INT_ENABLE, IXP2400_PCI_XSCALE_INT_PILM); intUnlock(locKey);#endif /*Since there are two processors on our system, the Master NPU will *have ProcNum as 0 and the slave NPU is 0 */ if(isNPUMaster()) sysProcNumSet(0); else sysProcNumSet(1);#if defined (INCLUDE_PCI) /* Initialize the ADUC812 micro controller which does the Voltage and * Temperature monitoring */ if(boardRev > 3) { if(isNPUMaster()) aduc812Init(); }#endif sysLEDDisplay('H', 'W', 'U','P'); locKey = intLock(); /*Now take MSF out of reset*/ IXP2400_REG_WRITE(IXP2400_RESET_0,0x00208080); IXP2400_REG_WRITE(IXP2400_RESET_0,0x00208000);#if A0_REV /*set the rcomp values for the MSF*/ IXP2400_REG_WRITE((IXP2400_MSF_CSR_BASE+0xFC), 0x15291E); IXP2400_REG_WRITE((IXP2400_MSF_CSR_BASE+0xF8), 0x15291E);#endif /* now we are done with the hw init, so set the system LED*/ IXP2400_REG_WRITE(SYSTEM_LED,0x0); intUnlock(locKey);}/********************************************************************************* sysPhysMemTop - get the address of the top of physical memory** This routine returns the address of the first missing byte of memory,* which indicates the top of memory.** Normally, the user specifies the amount of physical memory with the* macro LOCAL_MEM_SIZE in config.h. BSPs that support run-time* memory sizing do so only if the macro LOCAL_MEM_AUTOSIZE is defined.* If not defined, then LOCAL_MEM_SIZE is assumed to be, and must be, the* true size of physical memory.** NOTE: Do no adjust LOCAL_MEM_SIZE to reserve memory for application* use. See sysMemTop() for more information on reserving memory.** RETURNS: The address of the top of physical memory.** SEE ALSO: sysMemTop()*/char *sysPhysMemTop (void) { static char * physTop = NULL; if (physTop == NULL) {#ifdef LOCAL_MEM_AUTOSIZE /* If auto-sizing is possible, this would be the spot. */# error "Dynamic memory sizing not supported"#else /* Don't do autosizing, if size is given */ physTop = (char *)(LOCAL_MEM_LOCAL_ADRS + LOCAL_MEM_SIZE);#endif /* LOCAL_MEM_AUTOSIZE */ } return physTop; }/********************************************************************************* sysMemTop - get the address of the top of memory** This routine returns the address of the first missing byte of memory,* which indicates the top of memory.** RETURNS: The address of the top of memory.*/char *sysMemTop (void) { return ((char *)LOCAL_MEM_LOCAL_ADRS + (LOCAL_MEM_SIZE - USER_RESERVED_MEM)); }/********************************************************************************* sysToMonitor - transfer control to the ROM monitor** This routine transfers control to the ROM monitor. It is usually called* only by reboot() -- which services ^X -- and bus errors at interrupt* level. However, in some circumstances, the user may wish to introduce a* new <startType> to enable special boot ROM facilities.** startType - passed to ROM to tell it how to boot** RETURNS: Does not return.*/STATUS sysToMonitor (int startType) { FUNCPTR pRom; #if defined(INCLUDE_END) END_OBJ * pEnd; UINT32 i; #endif /* INCLUDE_END */ sysLEDDisplay('R','S','E','T'); #if defined(INCLUDE_END) /* * If the Ethernet driver were left alone, the controller chip might * alter memory, so we stop the controller before jumping to the bootrom. */ for(i = 0; i < PCI_MAX_DEV; i++) { if ( (pEnd = (END_OBJ *)endFindByName ("fei", i)) != NULL) pEnd->pFuncTable->stop(pEnd->devObject.pDevice); } #endif /* INCLUDE_END */ IXP2400_REG_WRITE(IXP2400_IRQ_ENABLE_CLR_REG,IXP2400_MASK_ALL_INT); sysClkDisable(); #if defined(INCLUDE_SERIAL) sysSerialReset (); /* put serial devices into quiet state */ #endif intIFLock (); cacheArmXSCALEDClearDisable (); cacheArmXSCALEIClearDisable (); /*I think we should also set the BOOT_DONT_INIT_PCI in register R0 */ startType |= BOOT_DONT_INIT_PCI; /*when bootrom is booted through Boot Monitor, jump to bootrom in flash*/ if ((vxWorksTextAddr == (BOOTROM_OFFSET - IXP2400_FLASH_BASE)) || (vxWorksTextAddr == (BOOTROM_TEXT_ADRS - IXP2400_FLASH_BASE))) { startType |= BOOTROM_THRU_BM; startType |= BOOT_THRU_BM; if (!(startType & BOOT_COLD)) pRom = (FUNCPTR) (BOOTROM_TEXT_ADRS+4); /* warm boot */ else pRom = (FUNCPTR) (BOOTROM_TEXT_ADRS); /* cold boot */ (*pRom)(startType); /* jump to boot ROM */ } /*when Vxworks_rom is loaded into SDRAM by Boot Monitor, reset the entire system*/ if(vxWorksTextAddr != 0) { if(strapOptionsVal & CFG_PCI_BOOT_HOST) /*is NPU has MASTER*/ *((volatile UINT32 *)IXP2400_RESET_0) |= (1 << 16); else /*slave*/ *(volatile UINT32 *)(IXP2400_MAILBOX0) = 0x1; IXP2400_REG_WRITE(IXP2400_PCI_CONTROL, IXP2400_PCI_CONTROL_XS_INT); } if(strapOptionsVal & CFG_PROM_BOOT) /*is NPU has flash*/ { if (!(startType & BOOT_COLD) ) pRom = (FUNCPTR) (ROM_TEXT_ADRS + 4); /* warm boot */ else pRom = (FUNCPTR) (ROM_TEXT_ADRS); /* cold boot */ (*pRom)(startType); /* jump to boot ROM */ } else /*if single flash*/ { *(volatile UINT32 *)(IXP2400_MAILBOX0) = 0x2; IXP2400_REG_WRITE(IXP2400_PCI_CONTROL, IXP2400_PCI_CONTROL_XS_INT); } return OK; /* in case we ever continue from ROM monitor */}/*** BSP Info Routines ***//****************************************************************************** sysProcNumGet - get the processor number** This routine returns the processor number for the CPU board, which is* set with sysProcNumSet().** RETURNS: The processor number for the CPU board.** SEE ALSO: sysProcNumSet()*/int sysProcNumGet (void) { return sysProcNum; }
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